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SI8220BD-D-ISR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
Si8220/21
Rev. 1.2 25
12. Package Outline: 16-Pin Wide Body SOIC
Figure 20 illustrates the package details for the Si822x Digital Isolator. Table 17 lists the values for the dimensions
shown in the illustration.
Figure 20. 16-Pin Wide Body SOIC
Si8220/21
26 Rev. 1.2
Table 17. Package Diagram Dimensions
Dimension
Min Max
A — 2.65
A1 0.10 0.30
A2 2.05 —
b 0.31 0.51
c 0.20 0.33
D 10.30 BSC
E 10.30 BSC
E1
7.50 BSC
e
1.27 BSC
L 0.40 1.27
h 0.25 0.75
0° 8°
aaa
—0.10
bbb — 0.33
ccc
—
0.10
ddd — 0.25
eee
—
0.10
fff
—
0.20
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AA.
4. Recommended reflow profile per JEDEC J-STD-020C specification for
small body, lead-free components.
Si8220/21
Rev. 1.2 27
13. Land Pattern: 16-Pin Wide-Body SOIC
Figure 21 illustrates the recommended land pattern details for the Si822x in a 16-pin wide-body SOIC. Table 18
lists the values for the dimensions shown in the illustration.
Figure 21. 16-Pin SOIC Land Pattern
Table 18. 16-Pin Wide Body SOIC Land Pattern Dimensions
Dimension Feature (mm)
C1 Pad Column Spacing 9.40
E Pad Row Pitch 1.27
X1 Pad Width 0.60
Y1 Pad Length 1.90
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

SI8220BD-D-ISR

Mfr. #:
Buy SI8220BD-D-ISR
Manufacturer:
Silicon Labs
Description:
Gate Drivers 5 kV opto input isolated gate driver
Lifecycle:
New from this manufacturer.
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