LTC4231
10
4321fa
For more information www.linear.com/LTC4231
The micropower capability of the LTC4231 makes it ideal for
Hot Swap applications in battery powered systems where
current load is light or intermittent and power draw is a
concern. It can implement battery short circuit protection,
reverse battery protection, battery voltage monitoring,
power path control, hot-plug and inrush current control
in off-grid, autonomous systems.
Turn-On Sequence
When IN is less than the UVLO level of 2.3V or SHDN is
low, GATE is pulled to GND and STATUS pulls low. When
IN ≥ 2.3V and SHDN goes high, an internal clock starts
timing a 40ms debounce cycle. The clock also times a
200µs strobe of the resistive divider at IN every 10ms
to make sure IN is not in OV/UV. Average I
CC
during this
debounce mode is 4µA.
Any OV/UV detected will stop and reset the debounce timing
cycle. During this voltage fault mode, average I
CC
isA.
The debounce cycle only restarts when a subsequent IN
strobe indicates that the input power is within the accept
-
able range, IN ≥ 2.3V and SHDN is high.
When the debounce cycle of 40ms successfully completes,
the LTC4231 turns on its charge pump, analog current
limit
amplifier and TIMER control circuit blocks as it goes
applicaTions inForMaTion
into start-up mode (I
CC
= 300µA). The external MOSFET
is turned on by charging up the GATE with a 10μA charge
pump generated current source.
At start-up, the MOSFET current is typically dominated by
the current charging the load capacitor C
L
. IfV
SENSE
>
80mV, the analog current limit amplifier controls the gate
of the MOSFET in a closed loop. This keeps the start-up
inrush current at 80mV/R
SENSE
. When ∆V
SENSE
> 50mV,
the TIMER capacitor charges up with an internal 50µA
pull-up current.
Figure 2. Inrush Control by Analog Current Limit
SENSE GATE
IN
UVL
UVH
OV
GNDSW
SOURCE
STATUS
SHDN
TIMER
LTC4231
M1
Si7120ADN
R
SENSE
22.5mΩ
GND
R
STAT
20k
R5
2M
C1
1nF
R5
10Ω
C
G
20nF
V
OUT
24V
2A
GND
R1
1020k
Z1
SMAJ24A
C
IN
100µF
R2
1.65k
24V
BATTERY
CELL(S)
UV RISING = 23V
UV FALLING = 22V
OV RISING = 26V
R3
4.22k
R4
32.4k
C
T
39nF
I
LOAD
4231 F01
R
G
1k
R7
10M
+
+
C
L
1000µF
Figure 1. Channel Controller with Connector Enable
GATE
20V/DIV
OUT
20V/DIV
TIMER
0.5V/DIV
I
LOAD
2A/DIV
1ms/DIV
START-UP NORMAL ONDEBOUNCE
4231 F02
LTC4231
11
4321fa
For more information www.linear.com/LTC4231
applicaTions inForMaTion
In most applications, keeping the inrush current at ana-
log current limit is an acceptable start-up method if the
TIMER
delay is long enough to avoid setting the current
fault latch and the MOSFET has adequate safe operating
margin. However, for more flexibility in design (See the
Design Example section), a capacitor from GATE to GND
(Figure 1) can be used to limit the V
GATE
slew rate for inrush
current control. V
GATE
rises with a slope equal to 10μA/C
G
(Figure 3). The supply inrush current is then limited to:
I
INRUSH
=
C
L
C
G
10µA
OnceV
GATE
exceedsV
GATE(H)
, STATUS goes high imped-
ance. I
CC
drops from 300µA toA (average) during this
normal on mode as some circuit blocks are shut down
and the internal charge pump periodically turns on when
∆V
GATE
droops by 0.7V or every 15ms, whichever comes
first (Figure 7).
In the back-to-back MOSFET configuration as shown in
Figure 5, SOURCE will also be pulled to GND via the para-
sitic body
diode between GATE and SOURCE, cutting off
the
load from IN. This configuration is suitable in power
path control and reverse battery protection applications
where IN is likely to go below GND.
In the single MOSFET configuration (Figure 1), the 1mA
pull-down from GATE to GND also discharges the load
capacitor C
L
to GND once GATE goes below SOURCE.
Overcurrent Fault
The 50mV circuit breaker threshold sets the maximum load
current allowed under steady state conditions. However,
the LTC4231 allows mild overcurrents during supply or
load transients whenV
SENSE
momentarily exceeds 50mV
but stays below the 80mV analog current limit threshold.
For severe overcurrents whenV
SENSE
exceeds 80mV,
the analog current limit amplifier controlsV
GATE
to regu-
late
V
SENSE
to 80mV. The durations of these transient
overcurrents must be less than the circuit breaker delay
(t
CB
) which can be adjusted using the capacitor C
T
at the
TIMER pin.
WhenV
SENSE
exceeds 50mV, the LTC4231 goes into
overcurrent mode. C
T
is charged with a 50μA pull-up. If
the overcurrent is transient andV
SENSE
goes below 50mV
before TIMER reaches 1.193V, the 50μA pull-up on TIMER
switches to aA pull-down. Multiple overcurrents with
a duty cycle > 10% can thus eventually integrate TIMER
to 1.193V. When TIMER reaches 1.193V, the LTC4231
goes into current fault mode and sets an internal current
fault latch. The external MOSFET will be cut off by a 1mA
pull-down from GATE to GND while STATUS pull-down
is asserted.
The time in which LTC4231 stays in overcurrent mode
before going into current fault mode is called the circuit
breaker delay and is given by:
t
CB
= C
T
• 24 [ms/µF]
Figure 3. Inrush Control by Limiting V
GATE
Slew
GATE
20V/DIV
OUT
20V/DIV
I
LOAD
0.5A/DIV
20ms/DIV
4231 F03
START-UP NORMAL ON
DEBOUNCE
Turn-Off Sequence
The MOSFET switch can be turned off by SHDN going low,
an OV/UV event, an overcurrent setting the current fault
latch or IN dropping below its UVLO voltage. Under any
of these conditions, STATUS pulls low and the MOSFET
is turned off with a 1mA current pulling down from GATE
to GND.
LTC4231
12
4321fa
For more information www.linear.com/LTC4231
applicaTions inForMaTion
IN
SOURCE
GATE
SHDN
STATUS
VOLTAGE FAULT
∆V
SENSE
TIMER
GNDSW
DEBOUNCE
START-UP START-UPNORMAL ON
OVER-
CURRENT
CURRENT
FAULT
SHUT-
DOWN DEBOUNCE
NORMAL ON
4µA 4µA 4µA 4µA
300µA
300µA
300µA
AVERAGE
I
CC
200µs
0.3µA
4µA
(I
GATE(LEAKAGE)
≤ 0.1µA)
4µA
(I
GATE(LEAKAGE)
≤ 0.1µA)
V
OVOFF
40ms t
CB
40ms
4231 F04
∆V
SENSE(CB)
∆V
GATE(H)
0.7V
V
TIMER(H)
V
TIMER(L)
Figure 4. LTC4231-1 Overcurrent

LTC4231CMS-2#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers Micropower Hot Swap Controller with Auto-Retry
Lifecycle:
New from this manufacturer.
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