LTC4231
16
4321fa
For more information www.linear.com/LTC4231
applicaTions inForMaTion
Supply Transient Protection
When the capacitances at the input and output are very
small, rapid changes in current during an output short-
circuit event can cause transients that exceed the 40V
absolute maximum ratings of IN, SENSE and SOURCE.
To minimize such spikes, use wider traces or heavier
trace plating to reduce the power trace inductance. Also,
bypass locally with a 10μF electrolytic and 0.1μF ceramic
if hot plug inrush current is not a concern. Alternatively,
clamp the input with a transient voltage suppressor (Z1
in Figure 5). A 10Ω, 0.1μF snubber damps the response
and reduces ringing (R
X
and C
X
in Figure 5).
Design Example
As a design example, take the following specifications for
the Figure 5 application circuit. The application is rated
for a V
IN
of 24V at 2A, C
L
= 100µF. UV rising = 23V, UV
falling = 22V, OV rising = 26V.
Sense resistor:
R
SENSE
=
V
SENSE(CB)(MIN)
2A
=
47mV
2A
= 23.5m
Use R
SENSE
= 22.5 for margin. Worst case analog
current limit:
I
LIMIT(MIN)
=
V
SENSE(ACL)(MIN)
22.5m
=
65mV
22.5m
= 2.89A
I
LIMIT(MAX)
=
V
SENSE(ACL)(MAX)
22.5m
=
90mV
22.5m
= 4A
Calculate the worst case time it takes to charge up C
L
in
analog current limit:
t
CHARGE(MAX)
=
C
L
V
IN
I
LIMIT(MIN)
=
100µF 24V
2.89A
= 0.9ms
For inrush control using analog current limit, t
CHARGE(MAX)
must be less than the circuit breaker delay (t
CB
) for a
proper start-up.
The worst case power dissipation in MOSFET M1 occurs
during a severe overcurrent fault when the current is
controlled by analog current limit for the duration of t
CB
:
P
DISS
= V
IN
I
LIMIT(MAX)
= 24V • 4A = 96W
The SOA (safe operating area) curve for the Si7164DP
MOSFET shows that it can withstand 180W for 10ms. So
choose a t
CB
that is less than 10ms but higher than 0.9ms
(t
CHARGE(MAX)
). In this case, use t
CB
= 2ms.
C
T
=
t
CB
24
=
2ms
24
= 0.082µF = 82nF
If a low inrush current (< ∆V
SENSE(CB)
) is preferred, refer to
the Figure 1 application circuit which uses a gate capaci-
tor C
G
to limit the inrush current. Choose I
INRUSH
= 0.5A
which is set using C
G
:
C
G
=
C
L
I
INRUSH
10µA =
1000µF
0.5A
10µA = 20nF
The time to charge up C
L
with 0.5A is:
t
CHARGE
=
C
L
V
IN
I
INRUSH
=
1000µF 24V
0.5A
= 48ms
In this case t
CHARGE
can be longer than t
CB
with no start-
up issue.
The average power dissipation in the MOSFET M1 during
this start-up is:
P
DISS
=
V
IN
I
INRUSH
2
=
24V 0.5A
2
= 6W
The SOA of the MOSFET M1 must be evaluated to ensure
that it can withstand 6W for 48ms. The SOA curve of the
Si7120ADN withstands 10W for 360ms, satisfying the
requirement.
The purpose of MOSFET M2 is to block the reverse path
from OUT (drain of M2) to IN when GATE pulls to GND so
that IN can go lower than OUT or even negative. Choose a
40V MOSFET to withstand a worse case reverse DC volt
-
age of
–24
V. The Si5410DU offers a good choice with a
maximum R
DS(ON)
of 18mΩ at V
GS
= 10V.
LTC4231
17
4321fa
For more information www.linear.com/LTC4231
applicaTions inForMaTion
The IN monitoring resistors R1–R4 should be chosen to
yield a total divider resistance of between 1M to 2M for
both low power and good transient response. Using the
formulas from the Monitor OV and UV Faults section,
R1–R4 are calculated as follows (with all resistor values
rounded up to the nearest 1% accurate standard values):
Choose R1 + R2 + R3 + R4 = 1000kΩ
R4 =
0.795V
V
OVOFF
1000k
Choose R4 = 32.4kΩ to give total divider resistance: R1
+ R2 + R3 + R4 = 1060kΩ.
R3 =
V
OVOFF
V
UVON
1
R4 =
26V
23V
1
32.4k = 4.22k
R2 =
V
UVON
V
UVOFF
1
V
OVOFF
V
UVON
R4
=
23V
22V
1
26V
23V
32.4k = 1.65k
R1=
V
OVOFF
0.795V
1
R4R3R2
=
26V
0.795V
1
32.4k4.22kΩ − 1.65k = 1020k
Layout Considerations
To achieve accurate current sensing, a Kelvin connection
for the sense resistor is recommended. The PCB layout
for the resistor should be balanced and symmetrical to
minimize wiring errors. In addition, the PCB layout for the
sense resistors and the power MOSFETs should include
good thermal management techniques for optimal device
power dissipation. In Hot Swap applications where load
currents can be high, narrow PCB tracks exhibit more
resistance than wider tracks and operate at elevated tem
-
peratures. 1oz copper
exhibits a sheet resistance of about
0.5mΩ/square. The minimum trace width for 1oz copper
foil is 0.5mm per amp to make sure the trace stays at a
reasonable temperature. Using 0.8mm per amp or wider
is recommended. Thicker top and bottom copper such as
3oz or more can improve electrical conduction and reduce
PCB trace dissipation.
If a resistor R5 (see Figure 1) is used, place it as close as
possible to M1's gate input. This will limit the parasitic
trace capacitance that leads to M1 self-oscillation. The
transient voltage suppressor, Z1, when used, should be
mounted close to the LTC4231 using short lead lengths.
A recommended PCB layout for the sense resistor and
back-
to back power MOSFETs is shown in Figure 9.
LTC4231
MOSFET M1
MOSFET M2
Z1
R
SENSE
R
STAT
R5
4231 F09
Figure 9. Recommended Layout
LTC4231
18
4321fa
For more information www.linear.com/LTC4231
applicaTions inForMaTion
SENSE GATE
IN
UVL
UVH
OV
GNDSW
SHDN
SOURCE
STATUS
TIMER
LTC4231
LTC2955-1
M1
Si7120ADN
INT
EN
KILL
TIMER
ON
V
IN
PB
Z1
SMAJ28CA
R
SENSE
45mΩ
M2
Si5410DU OUT
GND
C
L
100µF
UV RISING = 25V
UV FALLING = 24V
OV RISING = 28.5V
V
OUT
25V
1A
R1
1070k
R
IN
10k
C
IN
100nF
R2
1.47k
25V
R3
4.32k
R
STAT
4.7M
R4
30.9k
GND
C
T
180nF
C2
180nF
4231 F10
Figure 10. Micropower Push Button and Hot Swap Controllers with Reverse Battery Protection
Additional Applications
Figure 10 shows a reverse-battery protected application
featuring the LTC2955 micropower push-button controller.
A press on the push button switch will turn on the LTC4231
while a subsequent press will turn off the LTC4231. In the
event the LTC4231 is unable to power-up successfully
when EN goes high, the STATUS output is fed back to the
KILL input in order to place the LTC4231 back in the very
low-power Shutdown mode.
Figure 11 illustrates a 36V application with an UV rising
threshold of 35V, an UV falling threshold of 33V and an
OV rising threshold of 38V. As the IN operating voltage
is so near to its 40V absolute maximum rating, a suitable
TransZorb is not available to protect IN. Instead, a float
-
ing GND
architecture is used to help the LTC4231 survive
p
ossible voltage transients during short circuit events. This
architecture is strictly for handling IN transients during
36V operation. It does not allow DC V
IN
operation > 39V.

LTC4231CMS-2#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers Micropower Hot Swap Controller with Auto-Retry
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union