LTC4231
13
4321fa
For more information www.linear.com/LTC4231
applicaTions inForMaTion
Auto-Retry vs Latchoff
During current fault mode, GATE is held low and TIMER is
discharged to GND. Once TIMER < 0.1V, average I
CC
goes
toA and the internal current fault latch is ready to be
reset. The LTC4231-2 (automatic retry) waits for a 500ms
retry delay after which the internal current fault latch is
reset and GATE ramps up to turn the MOSFET back on.
The LTC4231-1 (latchoff) version does not restart automati
-
cally. Pulling SHDN low for >100µs will reset the internal
current fault latch. When SHDN goes high, GATE ramps
up after a debounce cycle. Alternatively, IN can be pulled
to GND for >100µs then cycled back up again. This UVLO
event will reset the internal current fault latch and GATE
ramps up after a debounce cycle. A UV/OV detected at IN
also resets the internal current fault latch and GATE ramps
up after a debounce delay.
Analog Current Limit Loop Stability
The analog current limit loop on GATE is compensated by
the parasitic gate capacitance of the external MOSFET. No
further compensation components are normally required.
If a small MOSFET with C
ISS
≤ 1nF is chosen, an R
G
and
C
G
compensation network connected at GATE may be
required (Figure 1) to ensure stability. The resistor, R
G
,
connected in series with C
G
accelerates the MOSFET gate
recovery after a fast gate pull-down. The value of C
G
should
be ≤100nF. An additional 10Ω resistor (R5 in Figure 1)
should be added close to the MOSFET gate to prevent
possible parasitic oscillation due to trace/wire inductance
and capacitance.
Monitor OV and UV Faults
When IN is above UVLO and SHDN is high, an internal
clock times a 200µs strobe of the resistive divider at IN
every 10ms. During this 200µs strobe, the normally high
impedance GNDSW is connected to GND with an internal
80Ω switch and the comparators connected to UVH, UVL
and OV are awakened from sleep mode. The comparators
sense the voltages on the resistive divider, and their outputs
are latched at the end of the strobe window.
If an OV or UV violation is detected, the STATUS pulls
low and a 1mA pull-down will be activated between GATE
and GND to turn off the external MOSFET. When GATE
goes <1.2V, average I
CC
drops toA as the LTC4231
goes into voltage fault mode. It stays in this mode until a
subsequent IN
strobe sees no OV/UV. The LTC4231 then
re-starts after a debounce cycle.
Strobing the resistive divider reduces power consumption
as the external resistors as well as the internal OV/UV
comparators do not dissipate power in between strobes.
For a 1M string of resistors used to monitor a V
IN
of 24V,
this strobing scheme reduces the current consumption
from 24µA to 0.48µA as the strobing duty cycle is 2%
(200µs/10ms). The OV/UV comparators dissipate 35µA
during IN strobing. The 2% duty cycle reduces this to an
average current of 0.7µA. Note that the response time to
an OV/UV event can be as long as 10ms.
The four resistors allow three thresholds to be configured.
They are the UV rising threshold (V
UVON
), the UV falling
threshold (V
UVOFF
) and the OV rising threshold (V
OVOFF
).
The OV falling threshold is set by internal hysteresis to be
1.8% below the OV rising threshold. Using the compara
-
tor threshold as 0.795V and choosing appropriate values
for R
TOTAL
and R4, the resistor values can be calculated
as follows:
R
TOTAL
= R1+R2+ R3+R4
R4 =
0.795V
V
OVOFF
R
TOTAL
R3 =
V
OVOFF
V
UVON
1
R4
R2 =
V
UVON
V
UVOFF
1
V
OVOFF
V
UVON
R4
R1=
U
OVOFF
0.795V
1
R4R3R2
It is recommended that the total value of the resistor
string be less than 2M and traces at UVH, UVL, and OV
kept short to minimize parasitic capacitance and improve
settling time.
LTC4231
14
4321fa
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applicaTions inForMaTion
Reverse Input Protection
Negative voltages at IN can occur if a battery is plugged
in backwards or a negative supply is inadvertently con
-
nected. Back-to-back N-channel MOSFETs can be used as
in Figure 5 to prevent the negative voltage from passing
to the output load.
IN, SENSE, GATE and SOURCE are protected against reverse
inputs of up to –40V. When the LTC4231's reverse volt
-
age comparators
detect a negative voltage at SENSE, an
internal switch is activated to connect GATE to SENSE. The
body diode of M1 pulls SOURCE to a diode above SENSE.
Since M2 is off and its body diode is in the reverse blocking
mode, the negative voltage is blocked by the V
DS
of M2.
Figure 6 shows the waveforms when the application circuit
in Figure 5 is hot plugged to –24V. Due to the parasitic
inductance at IN, SENSE and GATE, the voltages ring
significantly below –24V. The TransZorb helps to clamp
the negative undershoot and a 40V MOSFET is selected
for M2 to survive this undershoot.
Figure 5. Back-to-Back MOSFETs Protect Against Reverse Input
Figure 6. LTC4231 in Reverse Input Mode
SENSE GATE
IN
UVL
UVH
OV
GNDSW
SOURCE
STATUS
SHDN
TIMER
LTC4231
M1
Si7164DP
Z1
SMAJ24CA
R
SENSE
22.5mΩ
M2
Si5410DU
GND
R
STAT
20k
C
L
100µF
UV RISING = 23V
UV FALLING = 22V
OV RISING = 26V
V
OUT
24V
2A
R1
1020k
R
X
10Ω
C
X
0.1µF
R2
1.65k
24V
R3
4.22k
R4
32.4k
C
T
82nF
I
LOAD
4231 F05
GATE
20V/DIV
OUT
20V/DIV
IN
20V/DIV
1µs/DIV
4231 F06
LTC4231
15
4321fa
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applicaTions inForMaTion
Achieving Low Quiescent Current
Table 1 summarizes the average I
CC
of the various operat-
ing modes of the LTC4231.
Table 1
MODE I
CC
(NORM) I
CC
(MAX)
Start-Up or Overcurrent 300µA 600µA
Debounce, Normal On, Voltage or
Current Fault
4µA 10µA
Shutdown 0.3µA 1µA
Reverse Input –2.5mA –5mA
To lower I
CC
when GATE is high, the LTC4231 operates in
normal on mode, where the charge pump delivers pulses
of current to the GATE capacitance (either an external C
G
or the parasitic capacitance of the external MOSFETs)
to boostV
GATE
toV
GATE(H)
followed by sleep periods
when the GATE capacitance holds up GATE. Leakage will
causeV
GATE
to droop during these sleep periods. When
theV
GATE
low comparator detectsV
GATE
drooping by
more than 0.7V, it will activate the charge pump to boost
∆V
GATE
back toV
GATE(H)
before returning to sleep mode.
In addition to theV
GATE
low comparator, there is a charge
pump refresh timer that turns on the charge pump every
15ms to boostV
GATE
back toV
GATE(H)
. This timer is
reset when the charge pump turns on.
When in charge pump sleep mode the LTC4231 consumes
2µA. When the charge pump is on to deliver a current pulse
Figure 7. Regulating ∆V
GATE
During Normal On Mode Figure 8. SHDN Going Low Activates Shutdown Mode
V
GATE
2V/DIV
I
CC
200µA/DIV
5ms/DIV
4231 F07
I
GATE
= –0.1µA I
GATE
= –1µA
GATE
20V/DIV
SOURCE
20V/DIV
STATUS
20V/DIV
SHDN
5V/DIV
20µs/DIV
ENTERS
SHUTDOWN MODE
4231 F08
to GATE, I
CC
briefly goes up to 200µA. The amount of leak-
age at GATE (I
GATE(LEAKAGE)
) will determine the duty cycle
of the charge pump. Figure 7 shows start-up and ∆V
GATE
regulation (with different I
GATE(LEAKAGE)
) waveforms from
the Figure 5 application circuit.
As the average current delivered to GATE during the cur
-
rent pulse is around 15µA, the duty cycle of the charge
pump for a I
GATE(LEAKAGE)
of 0.1µA is 0.1/15 = 0.67%. The
average current due toV
GATE
regulation is then 0.67%
200µA = 1.3µA. When added to the average current
due to OV/UV strobing (0.7µA) and charge pump sleep
mode current (2µA), the average quiescent current of the
LTC4231 during the normal on mode is 1.3µA + 0.7µA +
2µA = 4µA. The normal on mode average supply current
can be estimated using the formula:
I
CC
= 2.7µA + 13.3 I
GATE(LEAKAGE)
The Typical Performance Characteristics section shows a
graph of average I
CC
(normal on) against I
GATE(LEAKAGE)
.
Shutdown Mode
When SHDN goes low, STATUS pulls low and a 1mA
pull-down will be activated between GATE and GND to
cut off the external MOSFET. When GATE reaches <1.2V,
I
CC
drops to 0.3µA as the LTC4231 goes into shutdown
mode. When SHDN goes high, GATE ramps up after the
40ms debounce cycle. Figure 8 shows the application in
Figure 5 going into shutdown mode.

LTC4231IMS-1#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers Micropower Hot Swap Controller with Latchoff
Lifecycle:
New from this manufacturer.
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