CY28346
......................Document #: 38-07331 Rev. *C Page 10 of 19
PCI_STP# Assertion
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (t
setup
) (see
Figure 14.) The PCI_F (0:2) clocks will not be affected by this
pin if their control bits in the SMBus register are set to allow
them to be free running.
Table 7. Cypress Clock Power Management Truth Table
B0b6 B1b6 PD# CPU_STP# Stoppable CPUT Stoppable
CPUC
Non-Stop CPUT Non-Stop CPUC
0 0 1 1 Running Running Running Running
0 0 1 0 Iref x6 Iref x6 Running Running
0 0 0 1 Iref x2 LOW Iref x2 LOW
0 0 0 0 Iref x2 LOW Iref x2 LOW
0 1 1 1 Running Running Running Running
0 1 1 0 Hi-Z Hi-Z Running Running
0 1 0 1 Hi-Z Hi-Z Hi-Z Hi-Z
0 1 0 0 Hi-Z Hi-Z Hi-Z Hi-Z
1 0 1 1 Running Running Running Running
1 0 1 0 Iref x6 Iref x6 Running Running
1 0 0 1 Hi-Z Hi-Z Hi-Z Hi-Z
1 0 0 0 Hi-Z Hi-Z Hi-Z Hi-Z
1 1 1 1 Running Running Running Running
1 1 1 0 Hi-Z Hi-Z Running Running
1 1 0 1 Hi-Z Hi-Z Hi-Z Hi-Z
1 1 0 0 Hi-Z Hi-Z Hi-Z Hi-Z
CPU_STP#
CPUT
CPUC
CPUT
CPUC
Figure 10. CPU_STP# Deassertion Waveform
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......................Document #: 38-07331 Rev. *C Page 11 of 19
PCI_STP# – Deassertion (transition from logic “0”
to logic “1”)
The deassertion of the PCI_STP# signal will cause all PCI(0:6)
and stoppable PCI_F(0:2) clocks to resume running in a
synchronous manner within two PCI clock periods after
PCI_STP# transitions to a HIGH level.
Note. The PCI STOP function is controlled by two inputs. One
is the device PCI_STP# pin number 34 and the other is SMBus
Byte 0,Bit 3. These two inputs to the function are logically
AND’ed. If either the external pin or the internal SMBus
register bit is set LOW, the stoppable PCI clocks will be
stopped in a logic LOW state. Reading SMBus Byte 0,Bit 3 will
return a 0 value if either of these control bits are set LOW
(which indicates that the devices stoppable PCI clocks are not
running).
PD# (Power-down) Clarification
The PD# (power-down) pin is used to shut off all clocks prior
to shutting off power to the device. PD# is an asynchronous
active LOW input. This signal is synchronized internally to the
device powering down the clock synthesizer. PD# is an
asynchronous function for powering up the system. When PD#
is LOW, all clocks are driven to a LOW value and held there
and the VCO and PLLs are also powered down. All clocks are
shut down in a synchronous manner so has not to cause
glitches while transitioning to the LOW “stopped” state.
PD# – Assertion
When PD# is sampled LOW by two consecutive rising edges
of the CPUC clock, then on the next HIGH-to-LOW transition
of PCIF, the PCIF clock is stopped LOW. On the next
HIGH-to-LOW transition of 66Buff, the 66Buff clock is stopped
LOW. From this time, each clock will stop LOW on its next
HIGH-to-LOW transition, except the CPUT clock. The CPU
clocks are held with the CPUT clock pin driven HIGH with a
value of 2 × Iref, and CPUC undriven. After the last clock has
stopped, the rest of the generator will be shut down.
PD# – Deassertion
The power-up latency between PD# rising to a valid logic ‘1’
level and the starting of all clocks is less than 3.0 ms.
PCI_STP#
PCI_F(0:2) 33M
PCI(0:6) 33M
setup
t
Figure 11. PCI_STP# Assertion Waveform
PCI_STP#
PCI_F(0:2)
PCI(0:6)
setup
t
Figure 12. PCI_STP# Deassertion Waveform
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66Buff[0..2]
PCIF
PWRDWN#
CPU 133MHz
CPU# 133MHz
3V66
66In
REF 14.318MHz
USB 48MHz
Figure 13. Power-down Assertion Timing Waveforms Figure—Buffered Mode
PCI 33MHz
PWRDWN#
CPUT(0:2) 133MHz
CPUC(0:2) 133MHz
REF 14.318MHz
USB 48MHz
3V66
Figure 14. Power-down Assertion Timing Waveforms—Unbuffered Mode

CY28346ZCT

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Clock Synthesizer / Jitter Cleaner NB clk for Intel 830M & 845 chipsets (CK-408)
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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