........................Document #: 38-07331 Rev. *C Page 9 of 19
PCI_F and IOAPIC Clock Outputs
The PCIF clock outputs are intended to be used, if required,
for systems IOAPIC clock functionality. Any two of the PCI_F
clock outputs can be used as IOAPIC 33 Mhz clock outputs.
They are 3.3V outputs will be divided down via a simple
resistive voltage divider to meet specific system IOAPIC clock
voltage requirements. In the event that these clocks are not
required, they can be used as general PCI clocks or disabled
via the assertion of the PCI_STP# pin.
3V66_1/VCH Clock Output
The 3V66_1/VCH pin has a dual functionality that is selectable
Configured as DRCG (66M), SMBus Byte0, Bit 5 = “0”
The default condition for this pin is to power-up in a 66M
operation. In 66M operation this output is SSCG-capable and
when spreading is turned on, this clock will be modulated.
Configured as VCH (48M), SMBus Byte0, Bit 5 = “1”
In this mode, output is configured as a 48-Mhz non-spread
spectrum output that is phase-aligned with other 48M outputs
(USB and DOT) to within 1 ns pin-to-pin skew. The switching
of 3V66_1/VCH into VCH mode occurs at system power-on.
When the SMBus Bit 5 of Byte 0 is programmed from a “0” to
a “1,” the 3V66_1/VCH output may glitch while transitioning to
48M output mode.
The CPU_STP# signal is an active LOW input used to
synchronously stop and start the CPU output clocks while the
rest of the clock generator continues to function.
CPU_STP# – Assertion
When CPU_STP# pin is asserted, all CPUT/C outputs that are
set with the SMBus configuration to be stoppable via assertion
of CPU_STP# will be stopped after being sampled by two
falling CPUT/C clock edges. The final state of the stopped
CPU signals is CPUT = HIGH and CPU0C = LOW. There is no
change to the output drive current values during the stopped
state. The CPUT is driven HIGH with a current value equal to
(Mult 0 “select”) × (Iref), and the CPUC signal will not be
driven. Due to external pull-down circuitry CPUC will be LOW
during this stopped state.
The deassertion of the CPU_STP# signal will cause all
CPUT/C outputs that were stopped to resume normal
operation in a synchronous manner (meaning that no short or
stretched clock pulses will be produces when the clock
resumes). The maximum latency from the deassertion to
active outputs is no more than two CPUC clock cycles.
Three-state Control of CPU Clocks Clarification
During CPU_STP# and PD# modes, CPU clock outputs may
be set to driven or undriven (tri-state) by setting the corre-
sponding SMBus entry in Bit6 of Byte0 and Bit6 of Byte1.
Figure 8. Unbuffered Mode – 3V66(0:5) to PCI (0:6) and PCI_F(0:2) Phase Relationship
Figure 9. CPU_STP# Assertion Waveform