........................Document #: 38-07331 Rev. *C Page 7 of 19
Buffer Characteristics
Current Mode CPU Clock Buffer Characteristics
The current mode output buffer detail and current reference
circuit details are contained in the previous table of this data
sheet. The following parameters are used to specify output
buffer characteristics:
1. Output impedance of the current mode buffer circuit—Ro
(see Figure 4).
2. Minimum and maximum required voltage operation range
of the circuit—Vop (see Figure 4).
3. Series resistance in the buffer circuit—Ros (see Figure 4).
4. Current accuracy at given configuration into nominal test
load for given configuration.
Iout is selectable depending on implementation. The param-
eters above apply to all configurations. Vout is the voltage at
the pin of the device.
The various output current configurations are shown in the
host swing select functions table. For all configurations, the
deviation from the expected output current is ±7% as shown in
the current accuracy table.
Tr Tf
3.3V signals
ut under Tes
Load Cap
Figure 3. For Single-ended Output Signals
VDD3 (3.3V +/- 5%)
Vout = 1.2V max Vout
Slope ~ 1/R
Figure 4. Buffer Characteristics
........................Document #: 38-07331 Rev. *C Page 8 of 19
USB and DOT 48M Phase Relationship
The 48MUSB and 48MDOT clocks are in phase. It is under-
stood that the difference in edge rate will introduce some
inherent offset. When 3V66_1/VCH clock is configured for
VCH (48-MHz) operation it is also in phase with the USB and
DOT outputs. See Figure 5.
66IN to 66B(0:2) Buffered Prop Delay
The 66IN to 66B(0:2) output delay is shown in Figure 6.
The Tpd is the prop delay from the input pin (66IN) to the
output pins (66B[0:2]). The outputs’ variation of Tpd is
described in the AC parameters section of this data sheet. The
measurement taken at 1.5V.
66B(0:2) to PCI Buffered Clock Skew
Figure 7 shows the difference (skew) between the 3V33(0:5)
outputs when the 66M clocks are connected to 66IN. This
offset is described in the Group Timing Relationship and Toler-
ances section of this data sheet. The measurements were
taken at 1.5V.
3V66 to PCI Un-Buffered Clock Skew
Figure 8 shows the timing relationship between 3V66(0:5) and
PCI(0:6) and PCI_F(0:2) when configured to run in the unbuf-
fered mode.
Table 4. Host Clock (HCSL) Buffer Characteristics
Characteristic Min. Max.
Ro 3000 (recommended) N/A
Vout N/A 1.2V
Table 5. CPU Clock Current Select Function
Mult0 Board Target Trace/Term Z Reference R, Iref – Vdd (3*Rr) Output Current Voh @ Z
050 Rr = 221 1%, Iref = 5.00mA Ioh = 4*Iref 1.0V @ 50
150 Rr = 475 1%, Iref = 2.32mA Ioh = 6*Iref 0.7V @ 50
Table 6. Group Timing Relationship and Tolerances
Description Offset Tolerance Conditions
3V66 to PCI 2.5 ns 1.0 ns 3V66 Leads PCI (unbuffered mode)
48MUSB to 48MDOT Skew 0.0 ns 1.0 ns 0 degrees phase shift
66B(0:2) to PCI offset 2.5 ns 1.0 ns 66B Leads PCI (buffered mode)
Figure 5. 48MUSB and 48MDOT Phase Relationship
Figure 6. 66IN to 66B(0:2) Output Delay Figure
Figure 7. Buffer Mode – 33V66(0:1); 66BUF(0:2) Phase Relationship
........................Document #: 38-07331 Rev. *C Page 9 of 19
Special Functions
PCI_F and IOAPIC Clock Outputs
The PCIF clock outputs are intended to be used, if required,
for systems IOAPIC clock functionality. Any two of the PCI_F
clock outputs can be used as IOAPIC 33 Mhz clock outputs.
They are 3.3V outputs will be divided down via a simple
resistive voltage divider to meet specific system IOAPIC clock
voltage requirements. In the event that these clocks are not
required, they can be used as general PCI clocks or disabled
via the assertion of the PCI_STP# pin.
3V66_1/VCH Clock Output
The 3V66_1/VCH pin has a dual functionality that is selectable
via SMBus.
Configured as DRCG (66M), SMBus Byte0, Bit 5 = “0”
The default condition for this pin is to power-up in a 66M
operation. In 66M operation this output is SSCG-capable and
when spreading is turned on, this clock will be modulated.
Configured as VCH (48M), SMBus Byte0, Bit 5 = “1”
In this mode, output is configured as a 48-Mhz non-spread
spectrum output that is phase-aligned with other 48M outputs
(USB and DOT) to within 1 ns pin-to-pin skew. The switching
of 3V66_1/VCH into VCH mode occurs at system power-on.
When the SMBus Bit 5 of Byte 0 is programmed from a “0” to
a “1,” the 3V66_1/VCH output may glitch while transitioning to
48M output mode.
CPU_STP# Clarification
The CPU_STP# signal is an active LOW input used to
synchronously stop and start the CPU output clocks while the
rest of the clock generator continues to function.
CPU_STP# – Assertion
When CPU_STP# pin is asserted, all CPUT/C outputs that are
set with the SMBus configuration to be stoppable via assertion
of CPU_STP# will be stopped after being sampled by two
falling CPUT/C clock edges. The final state of the stopped
CPU signals is CPUT = HIGH and CPU0C = LOW. There is no
change to the output drive current values during the stopped
state. The CPUT is driven HIGH with a current value equal to
(Mult 0 “select”) × (Iref), and the CPUC signal will not be
driven. Due to external pull-down circuitry CPUC will be LOW
during this stopped state.
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal will cause all
CPUT/C outputs that were stopped to resume normal
operation in a synchronous manner (meaning that no short or
stretched clock pulses will be produces when the clock
resumes). The maximum latency from the deassertion to
active outputs is no more than two CPUC clock cycles.
Three-state Control of CPU Clocks Clarification
During CPU_STP# and PD# modes, CPU clock outputs may
be set to driven or undriven (tri-state) by setting the corre-
sponding SMBus entry in Bit6 of Byte0 and Bit6 of Byte1.
Figure 8. Unbuffered Mode – 3V66(0:5) to PCI (0:6) and PCI_F(0:2) Phase Relationship
Figure 9. CPU_STP# Assertion Waveform


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