ADuM120N/ADuM121N Data Sheet
Rev. B | Page 16 of 19
APPLICATIONS INFORMATION
OVERVIEW
The ADuM120N/ADuM121N use a high frequency carrier to
transmit data across an isolation barrier using iCoupler chip
scale transformer coils separated by layers of polyimide
isolation. With an on/off keying (OOK) technique and the
differential architecture shown in Figure 13 and Figure 14, the
ADuM120N/ADuM121N have very low propagation delay and
high speed. Internal regulators and input/output design techniques
allow logic and supply voltages over a wide range from 1.7 V to
5.5 V, offering voltage translation of 1.8 V, 2.5 V, 3.3 V, and 5 V
logic. The architecture is designed for high common-mode
transient immunity and high immunity to electrical noise and
magnetic interference. Radiated emissions are minimized with a
spread spectrum OOK carrier and other techniques.
Figure 13 shows the operation block diagram of a single channel
for the ADuM120N0/ADuM121N0 models, which have the
condition of the fail-safe output state equal to low, where the
carrier waveform is off when the input state is low. If the input
side is off or not operating, the fail-safe output state of low
(noted by the 0 in the model number) sets the output to low.
For the ADuM120N1/ADuM121N1, which have a fail-safe output
state of high, Figure 14 shows the conditions where the carrier
waveform is off when the input state is high. When the input
side is off or not operating, the fail-safe output state of high
(noted by the 1 in the model number) sets the output to high.
See the Ordering Guide for the model numbers that have the
fail-safe output state of low or the fail-safe output state of high.
PCB LAYOUT
The ADuM120N/ADuM121N digital isolators require no external
interface circuitry for the logic interfaces. Power supply bypassing
is strongly recommended at the input and output supply pins
(see Figure 12). Bypass capacitors are most conveniently connected
between Pin 1 and Pin 4 for V
DD1
and between Pin 5 and Pin 8
for V
DD2
. The recommended bypass capacitor value is between
0.01 µF and 0.1 µF. The total lead length between both ends of
the capacitor and the input power supply pin must not exceed
10 mm.
V
DD1
V
IA/
V
OA
V
IB
V
DD2
V
OA/
V
IA
V
OB
GND
1
GND
2
14122-010
Figure 12. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling
that does occur equally affects all pins on a given component
side. Failure to ensure this can cause voltage differentials between
pins exceeding the Absolute Maximum Ratings of the device,
thereby leading to latch-up or permanent damage.
See the AN-1109 Application Note for board layout guidelines.
TRANSMITTER
GND
1
GND
2
V
IN
V
OUT
RECEIVER
REGULATOR REGULATOR
14122-011
Figure 13. Operational Block Diagram of a Single Channel with a Low Fail-Safe Output State
TRANSMITTER
GND
1
GND
2
V
IN
V
OUT
RECEIVER
REGULATOR
REGULATOR
14122-012
Figure 14. Operational Block Diagram of a Single Channel with a High Fail-Safe Output State
Data Sheet ADuM120N/ADuM121N
Rev. B | Page 17 of 19
PROPAGATION DELAY RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a Logic 0 output can differ from the propagation delay
to a Logic 1 output.
INPUT (V
Ix
)
OUTPUT (V
Ox
)
t
PLH
t
PHL
50%
50%
14122-013
Figure 15. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these
two propagation delay values and is an indication of how
accurately the timing of the input signal is preserved.
Channel matching is the maximum amount the propagation delay
differs between channels within a single ADuM120N/ADuM121N
component.
Propagation delay skew is the maximum amount the propagation
delay differs between multiple ADuM120N/ADuM121N
components operating under the same conditions
JITTER MEASUREMENT
Figure 16 shows the eye diagram for the ADuM120N/ADuM121N.
The measurement was taken using an Agilent 81110A pulse
pattern generator at 150 Mbps with pseudorandom bit sequences
(PRBS) 2(n − 1), n = 14, for 5 V supplies. Jitter was measured
with the Tektronix Model 5104B oscilloscope, 1 GHz, 10 GS/s
with the DPOJET jitter and eye diagram analysis tools. The result
shows a typical measurement on the ADuM120N/ADuM121N
with 380 ps p-p jitter.
105
0
1
2
3
4
VOLTAGE (V)
5
0
TIME (ns)
–5–10
14122-014
Figure 16. ADuM120N/ADuM121N Eye Diagram
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation as well as on the
materials and material interfaces.
The two types of insulation degradation of primary interest are
breakdown along surfaces exposed to the air and insulation wear
out. Surface breakdown is the phenomenon of surface tracking
and the primary determinant of surface creepage requirements
in system level standards. Insulation wear out is the phenomenon
where charge injection or displacement currents inside the
insulation material cause long-term insulation degradation.
Surface Tracking
Surface tracking is addressed in electrical safety standards by
setting a minimum surface creepage based on the working voltage,
the environmental conditions, and the properties of the insulation
material. Safety agencies perform characterization testing on the
surface insulation of components that allows the components to be
categorized in different material groups. Lower material group
ratings are more resistant to surface tracking and, therefore, can
provide adequate lifetime with smaller creepage. The minimum
creepage for a given working voltage and material group is in each
system level standard and is based on the total rms voltage
across the isolation, pollution degree, and material group. The
material group and creepage for the ADuM120N/ADuM121N
isolators are presented in Table 9.
Insulation Wear Out
The lifetime of insulation caused by wear out is determined by
the thickness, material properties, and the voltage stress applied.
It is important to verify that the product lifetime is adequate at
the application working voltage. The working voltage supported
by an isolator for wear out cannot be the same as the working
voltage supported for tracking. It is the working voltage applicable
to tracking that is specified in most standards.
Testing and modeling show that the primary driver of long-term
degradation is displacement current in the polyimide insulation
causing incremental damage. The stress on the insulation can be
broken down into broad categories, such as dc stress, which
causes very little wear out because there is no displacement
current, and an ac component time varying voltage stress,
which causes wear out.
ADuM120N/ADuM121N Data Sheet
Rev. B | Page 18 of 19
The ratings in certification documents are usually based on 60 Hz
sinusoidal stress because this the reflects isolation from line
voltage. However, many practical applications have combinations
of 60 Hz ac and dc across the barrier as shown in Equation 1.
Because only the ac portion of the stress causes wear out, the
equation can be rearranged to solve for the ac rms voltage, as is
shown in Equation 2. For insulation wear out with the polyimide
materials used in these products, the ac rms voltage determines
the product lifetime.
22
DCRMSACRMS
VVV +=
(1)
or
22
DCRMSRMSAC
VVV
=
(2)
where:
V
RMS
is the total rms working voltage.
V
AC RMS
is the time varying portion of the working voltage.
V
DC
is the dc offset of the working voltage.
Calculation and Use of Parameters Example
The following example frequently arises in power conversion
applications. Assume that the line voltage on one side of the
isolation is 240 V
AC RMS
and a 400 V
DC
bus voltage is present on
the other side of the isolation barrier. The isolator material is
polyimide. To establish the critical voltages in determining the
creepage, clearance, and lifetime of a device, see Figure 17 and
the following equations.
ISOLATION VOLTAGE
TIME
V
AC RMS
V
RMS
V
DC
V
PEAK
14122-015
Figure 17. Critical Voltage Example
The working voltage across the barrier from Equation 1 is
22
DCRMSACRMS
VVV +=
22
400240 +=
RMS
V
V
RMS
= 466 V
This is the working voltage used together with the material group
and pollution degree when looking up the creepage required by
a system standard.
To determine if the lifetime is adequate, obtain the time varying
portion of the working voltage. To obtain the ac rms voltage,
use Equation 2.
2
2
DC
RMS
RMSAC
VV
V
=
22
400466 =
RMSAC
V
V
AC RMS
= 240 V rms
In this case, the ac rms voltage is simply the line voltage of
240 V rms. This calculation is more relevant when the waveform is
not sinusoidal. The value is compared to the limits for working
voltage in Table 15 for the expected lifetime, less than a 60 Hz
sine wave, and it is well within the limit for a 50-year service life.
Note that the dc working voltage limit in Table 15 is set by the
creepage of the package as specified in IEC 60664-1. This value
can differ for specific system level standards.

ADUM120N1BRZ-RL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital Isolators 2ch EMC robust 3kV digital Isolator 2/0
Lifecycle:
New from this manufacturer.
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