AMIS−30522, NCV70522
http://onsemi.com
21
SPI INTERFACE
The serial peripheral interface (SPI) allows an external
microcontroller (Master) to communicate with the 522. The
implemented SPI block is designed to interface directly with
numerous micro−controllers from several manufacturers.
The 522 acts always as a Slave and cannot initiate any
transmission. The operation of the device is configured and
controlled by means of SPI registers which are observable
for read and/or write from the Master.
SPI Transfer Format and Pin Signals
During a SPI transfer, data is simultaneously transmitted
(shifted out serially) and received (shifted in serially). A
serial clock line (CLK) synchronizes shifting and sampling
of the information on the two serial data lines (DO and DI).
DO signal is the output from the Slave (522), and DI signal
is the output from the Master. A chip select line (CS
) allows
individual selection of a Slave SPI device in a multiple−
slave system. The CS
line is active low. If the 522 is not
selected, DO is pulled up with the external pullup resistor.
Since 522 operates as a Slave in MODE 0 (CPOL = 0; CPHA
= 0) it always clocks data out on the falling edge and samples
data in on rising edge of clock. The Master SPI port must be
configured in MODE 0 too, to match this operation. The SPI
clock idles low between the transferred bytes.
The diagram below is both a Master and a Slave timing
diagram since CLK, DO and DI pins are directly connected
between the Master and the Slave.
DI
MSB
CLK
1 2 3 4 5 6 7 8
DO
#CLK Cycle
MSB
LSB
LSB
654321
654321
Figure 17. Timing Diagram of a SPI Transfer
CS
NOTE: At the falling edge of the eighth clock pulse the data−out shift register is updated with the content of the addressed internal SPI
register. The internal SPI registers are updated at the first rising edge of the 522 system clock when CS
= High.
Transfer Packet
Serial data transfer is assumed to follow MSB first rule. The transfer packet contains one or more bytes.
LSB
DataCommand and SPI Register Address
CMD2 CMD1 CMD0 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
D7 D6 D5 D4 D3 D2 D1 D0
MSBLSBMSB
BYTE 1
BYTE 2
Command
SPI Register Address
Figure 18. SPI Transfer Packet
Byte 1 contains the Command and the SPI Register
Address and indicates to the 522 the chosen type of
operation and addressed register. Byte 2 contains data, or
sent from the Master in a WRITE operation, or received
from the 522 in a READ operation.
Two command types can be distinguished in the
communication between Master and 522:
• READ from SPI Register with address ADDR[4:0]:
CMD[2:0] = “000”
• WRITE to SPI Register with address ADDR[4:0]:
CMD[2:0] = “100”
