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22
READ Operation
If the Master wants to read data from Status or Control
Registers, it initiates the communication by sending a
READ command. This READ command contains the
address of the SPI register to be read out. At the falling edge
of the eighth clock pulse the dataout shift register is
updated with the content of the corresponding internal SPI
register. In the next 8bit clock pulse train this data is shifted
out via DO pin. At the same time the data shifted in from DI
(Master) should be interpreted as the following successive
command or dummy data.
Figure 19. Single READ Operation where DATA from SPI Register with Address 1 is Read by the Master
DATA from previous command or
NOT VALID after POR or RESET
Registers are updated with the internal status at the rising edge
of the internal AMIS30522/NCV70522 clock when CS
= 1
READ DATA from ADDR1 COMMAND or DUMMY
OLD DATA or NOT VALID DATA from ADDR1
COMMAND
DATA DATA
DO
DI
CS
All 4 Status Registers (see SPI Registers) contain 7 data
bits and an even parity check bit. The most significant bit
(D7) represents a parity of D[6:0]. If the number of logical
ones in D[6:0] is odd, the parity bit D7 equals “1”. If the
number of logical ones in D[6:0] is even then the parity bit
D7 equals “0”. This simple mechanism protects against
noise and increases the consistency of the transmitted data.
If a parity check error occurs it is recommended to initiate
an additional READ command to obtain the status again.
Also the Control Registers can be read out following the
same routine. Control Registers don’t have a parity check.
The CS
line is active low and may remain low between
successive READ commands as illustrated in Figure 21.
There is however one exception. In case an error condition
is latched in one of Status Registers (see SPI Registers) the
ERR
pin is activated. (See the “Error Output” Section). This
signal flags a problem to the external microcontroller. By
reading the Status Registers information, the root cause of
the problem can be determined. After this READ operation
the Status Registers are cleared. Because the Status
Registers and ERR
pin (see SPI Registers) are only updated
by the internal system clock when the CS
line is high, the
Master should force CS
high immediately after the READ
operation. For the same reason it is recommended to keep
the CS
line high always when the SPI bus is idle.
WRITE Operation
If the Master wants to write data to a Control Register it
initiates the communication by sending a WRITE
command. This contains the address of the SPI register to
write to. The command is followed with a data byte. This
incoming data will be stored in the corresponding Control
Register after CS
goes from low to high! AMIS30522/
NCV70522 responds on every incoming byte by shifting out
via DO the data stored in the last received address.
It is important that the writing action (command address
and data) to the Control Register is exactly 16 bits long. If
more or less bits are transmitted the complete transfer packet
is ignored.
A WRITE command executed for a readonly register
(e.g. Status Registers) will not affect the addressed register
and the device operation.
Because after a poweronreset the initial address is
unknown the data shifted out via DO is not valid.
DATA from previous command or
NOT VALID after POR or RESET
DO
DI
CS
WRITE DATA to ADDR3 NEW DATA for ADDR3
OLD DATA or NOT VALID
OLD DATA from ADDR3
COMMAND
DATA DATA
DATA
The NEW DATA is written into the corresponding
internal register at the rising edge of CS
Figure 20. Single WRITE Operation where DATA from the Master is Written in SPI Register with Address 3
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23
Examples of Combined READ and WRITE Operations
In the following examples successive READ and WRITE
operations are combined. In Figure 21 the Master first reads
the status from Register at ADDR4 and at ADDR5 followed
by writing a control byte in Control Register at ADDR2.
Note that during the write command (in Figures 20 and 21)
the old data of the pointed register is returned at the moment
the new data is shifted in.
Figure 21. Two Successive READ Commands Followed by a WRITE Command
COMMAND
COMMAND COMMAND
DATA
DATA
DATA DATA
DATA
DO
DI
CS
DATA from previous
command or NOT VALID
after POR or RESET
READ DATA
from ADDR4
READ DATA
from ADDR5
WRITE DATA
to ADDR2
NEW DATA
for ADDR2
OLD DATA
or NOT VALID
DATA
from ADDR4
DATA
from ADDR5
OLD DATA
from ADDR2
Registers are updated with the internal status at the rising
edge of the internal 522 clock when CS
= 1
The NEW DATA is written into the corresponding
internal register at the rising edge of CS
After the write operation the Master could initiate a read
back command in order to verify if the data is correctly
written, as illustrated in Figure 22. During reception of the
READ command the old data is returned for a second time.
Only after receiving the READ command the new data is
transmitted. This rule also applies when the master device
wants to initiate an SPI transfer to read the Status Registers.
Because the internal system clock updates the Status
Registers only when CS
line is high, the first read out byte
might represent old status information.
COMMAND
DATA DATA DATA DATA
OLD DATA
or NOT VALID
OLD DATA
from ADDR2
OLD DATA
from ADDR2
NEW DATA
from ADDR2
DO
DI
CS
Figure 22. A WRITE Operation where DATA from the Master is Written in SPI Register with Address 2 Followed by
a READ Back Operation to Verify a Correct WRITE Operation
DATA COMMAND
WRITE DATA
to ADDR2
NEW DATA
for ADDR2
READ DATA
from ADDR2
COMMAND or
DUMMY
Registers are Updated with the Internal
Status at the Rising Edge of CS
Registers are Updated with the In-
ternal Status at the Rising Edge of
the Internal 522 Clock when CS
= 1
DATA from previous
command or NOT VALID
after POR or RESET
NOTE: The internal dataout shift buffer of the AMIS30522/NCV70522 is updated with the content of the selected SPI register only at the
last (every eighth) falling edge of the CLK signal (see SPI Transfer Format and Pin Signals). As a result, new data for transmission
cannot be written to the shift buffer at the beginning of the transfer packet and the first byte shifted out might represent old data.
Table 11. SPI CONTROL REGISTERS
(All SPI Control Registers have Read/Write Access and default to “0” after Poweron or hard reset)
Address
Content
Structure
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
CRWD (00h) Data WDEN WDT[3:0] 0 0 0
CR0 (01h) Data SM[2:0] CUR[4:0]
CR1 (02h) Data DIRCTRL NXTP PWMF PWMJ EMC[1:0]
CR2 (03h) Data MOTEN SLP SLAG SLAT
Where:
R/W: Read and Write access
Reset: Status after PowerOn or hard reset
WDEN: Watchdog enable. Writing “0” to this bit will clear WD bit (see SPI Status Register 0)
WDT[3:0]: Watchdog timeout interval
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24
Table 12. SPI CONTROL PARAMETER OVERVIEW
Symbol Description Status Value
WDEN Watchdog enable.
<WDEN> = 1
Writing “1” to this bit will enable the watchdog timer (if not
enabled yet) or will clear this timer (if already enabled)
<WDEN> = 0 Writing “0” to this bit will disable the Watchdog
DIRCTRL
Controls the Direction of Rotation
(in Combination with Logic Level
on Input DIR)
<DIR> = 0
<DIRCTRL> = 0 CW Motion
<DIRCTRL> = 1 CCW Motion
<DIR> = 1
<DIRCTRL> = 0 CCW Motion
<DIRCTRL> = 1 CW Motion
EMC[1:0]
Turn On and Turnoff Slopes
(Note 15)
00 Very Fast
01 Fast
10 Slow
11 Very Slow
MOTEN Activates the Motor Driver Outputs
<MOTEN> = 0 Drivers Disabled
<MOTEN> = 1 Drivers Enabled
NXTP
Selects if NXT triggers on Rising
or Falling Edge
<NXTP> = 0 Trigger on Rising Edge
<NXTP> = 1 Trigger on Falling Edge
PWMF
Enables Doubling of the PWM
Frequency (Note 15)
<PWMF> = 0 Default Frequency
<PWMF> = 1 Double Frequency
PWMJ Enables Jitter PWM
<PWMJ> = 0 Jitter Disabled
<PWMJ> = 1 Jitter Enabled
SM[2:0] Stepmode
000 1/32 Micro Step
001 1/16 Micro Step
010 1/8 Micro Step
011 1/4 Micro Step
100 1/2 Compensated Half Step
101 1/2 Uncompensated Half Step
110 Full Step
111 n.a.
SLAG Speed Load Angle Gain Setting
<SLAG> = 0 Gain = 0.5
<SLAG> = 1 Gain = 0.25
SLAT
Speed Load Angle
Transparency Bit
<SLAT> = 0 SLA is NOT Transparent
<SLAT> = 1 SLA is Transparent
SLP Enables Sleep Mode
<SLP> = 0 Active Mode
<SLP> = 1 Sleep Mode
15.The typical values can be found in Table 5: DC Parameters and Table 6: AC Parameters

AMIS30522C5222G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Motor / Motion / Ignition Controllers & Drivers 800MA STEPPER DRVR
Lifecycle:
New from this manufacturer.
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