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950201AFLF

P1-P3P4-P6P7-P9P10-P12P13-P15
IDT
TM
Programmable Timing Control Hub
TM
for P4
TM
460J—01/25/10
ICS950201
Programmable Timing Control Hub
TM
for P4
TM
10
Electrical Characteristics - PCICLK
T
A
= 0 - 70°C; VDD=3.3V +/-5%; C
L
= 10-30 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Frequency F
O1
33.33 MHz
Output Impedance R
DSP1
1
V
O
= V
DD
*(0.5) 12 33 55 Ω
Output High Voltage V
OH
1
I
OH
= -1 mA 2.4 V
Output Low Voltage V
O
L
1
I
OL
= 1 mA 0.55 V
Output High Current
I
OH
1
V
OH@MIN
= 1.0 V, V
OH@MA
X
= 3.135 V -33 -33 mA
Output Low Current
I
OL
1
V
OL @MIN
= 1.95 V, V
OL @MA
X
= 0.4 V 30 38 mA
Rise Time t
r1
1
V
OL
= 0.4 V, V
OH
= 2.4 V 0.5 1.29 2 ns
Fall Time t
f1
1
V
OH
= 2.4 V, V
OL
= 0.4 V 0.5 1.45 2 ns
Duty Cycle
d
t1
1
V
T
= 1.5 V 45 51 55
%
Skew t
sk1
1
V
T
= 1.5 V 190 500 ps
Jitter,cycle to cyc
t
jcyc-cyc
1
V
T
= 1.5 V
124 250 ps
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
T
A
= 0 - 70°C; VDD=3.3V +/-5%; C
L
= 10-30 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Frequency F
O1
66.67 MHz
Output Impedance R
DSP1
1
V
O
= V
DD
*(0.5) 12 33 55
Ω
Output High Voltage V
OH
1
I
OH
= -1 mA 2.4 V
Output Low Voltage V
O
L
1
I
OL
= 1 mA 0.55 V
Output High Current
I
OH
1
V
OH@MIN
= 1.0 V, V
OH@MA
X
= 3.135 V -33 -33 mA
Output Low Current
I
OL
1
V
OL @MIN
= 1.95 V, V
OL @MA
X
= 0.4 V 30 38 mA
Rise Time t
r1
1
V
O
L
= 0.4 V, V
OH
= 2.4 V 0.5 1.28 2 ns
Fall Time t
f1
1
V
OH
= 2.4 V, V
O
L
= 0.4 V 0.5 1.36 2 ns
Duty Cycle
d
t1
1
V
T
= 1.5 V 45 53.1 55
%
Skew t
sk1
1
V
T
= 1.5 V 90 250 ps
Jitter
t
jcyc-cyc
1
V
T
= 1.5 V 3V66
128 250 ps
1
Guaranteed by design, not 100% tested in production.
IDT
TM
Programmable Timing Control Hub
TM
for P4
TM
460J—01/25/10
ICS950201
Programmable Timing Control Hub
TM
for P4
TM
11
All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no
defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard
skew described below as Tpci.
Un-Buffered Mode 3V66 & PCI Phase Relationship
3V66 (1:0)
3V66 (4:2)
3V66_5
PCICLK_F (2:0) PCICLK (6:0)
Tpci
Group Skews at Common Transition Edges: (Un-Buffered Mode)
GROUP SYMBOL CONDITIONS MIN TYP MAX UNITS
3V66 3V66 3V66 pin to pin skew 0 500 ps
PCI PCI PCI_F and PCI pin to pin skew 0 500 ps
3V66 to PCI S
3V66-PCI
3V66 leads 33MHz PCI 1.5 3.5 ns
1
Guaranteed by design, not 100% tested in production.
PD# Functionality
#POTS_UPCTUPCCUPC66V3TUO_zHM66
F_KLCICP
KLCICP
KLCICP
TOD/BSU
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M*feritaolFwoLwoLwoLwoLwoL
IDT
TM
Programmable Timing Control Hub
TM
for P4
TM
460J—01/25/10
ICS950201
Programmable Timing Control Hub
TM
for P4
TM
12
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low
in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising
edge.
PCI_STOP#
PCI_F[2:0] 33MHz
PCI[6:0] 33MHz
tsu
Assertion of PCI_STOP# Waveforms
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
CPU_STOP#
CPUT
CPUC
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I
2
C configuration to be stoppable via
assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown.
The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current
values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
Assertion of CPU_STOP# Waveforms
CPU_STOP# Functionality
#POTS_UPCTUPCCUPC
1lamroNlamroN
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P1-P3P4-P6P7-P9P10-P12P13-P15

950201AFLF

Mfr. #:
Buy 950201AFLF
Manufacturer:
IDT
Description:
Clock Generators & Support Products PC MAIN CLOCK
Lifecycle:
New from this manufacturer.
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