IDT
TM
Programmable Timing Control Hub
TM
for P4
TM
460J—01/25/10
ICS950201
Programmable Timing Control Hub
TM
for P4
TM
4
Host Swing Select Functions
Maximum Allowed Current
Truth Table
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IDT
TM
Programmable Timing Control Hub
TM
for P4
TM
460J—01/25/10
ICS950201
Programmable Timing Control Hub
TM
for P4
TM
5
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact IDT for an I
2
C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends a dummy command code
ICS clock will
acknowledge
Controller (host) sends a dummy byte count
ICS clock will
acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will
acknowledge
each byte
one at a
time
.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the
byte count
Controller (host) acknowledges
ICS clock sends first byte
(Byte 0) through byte 6
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Controller (Host) ICS (Slave/Receiver)
St art Bit
Address
D2
(H )
AC
K
Dummy Command Code
AC
K
Dummy Byte Count
AC
K
Byte 0
AC
K
Byte 1
AC
K
Byte 2
AC
K
Byte 3
AC
K
B
y
te 4
AC
K
B
y
te 5
AC
K
B
y
te 6
ACK
Stop Bit
How to Write:
Controller (Host) ICS (Slave/Receiver)
St art Bit
Address
D3
(H )
AC
K
Byte Coun
t
ACK
Byte
0
ACK
Byte 1
ACK
Byte
2
ACK
Byte
3
ACK
Byte
4
ACK
Byte
5
ACK
Byte
6
ACK
Stop Bit
How to Read:
1. The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has
been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two
bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
Notes:
IDT
TM
Programmable Timing Control Hub
TM
for P4
TM
460J—01/25/10
ICS950201
Programmable Timing Control Hub
TM
for P4
TM
6
Byte 0: Control Register
Byte 1: Control Register
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways. Wither the
system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert PCI_STOP
functionality via I
2
C Byte 0 Bit 3.
In Hardware mode it is not allowed to write to the I
2
C Byte 0 Bit3. In Software mode it is not allowed to pull the external
PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped PCI_STOP conditions.
The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it is not allowed to mix these
modes.
In Hardware mode the I
2
C byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip is in
PCI_STOP mode.
Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (I
2
C Byte 0 Bit 3 = 0)].
4. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high, CPUCLKC
off, and external resistor termination will bring CPUCLKC low.
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950201AFLF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products PC MAIN CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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