MT36HTF25672PY-667DZES Datasheet MT36HTF25672PY-40EB1, MT36HTF25672PY-53EB1, MT36HTF25672PY-667D1 | P7-P9

PDF: 09005aef818e3fc8/Source: 09005aef818e3fdb Micron Technology, Inc., reserves the right to change products or specifications without notice.

HTF36C256_512x72.fm - Rev. C 1/07 EN

2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM

General Description

The MT36HTF25672(P) and MT36HTF51272(P) DDR2 SDRAM modules are high-speed,

CMOS, dynamic random-access 2GB and 4GB memory modules, organized in x72

configurations. These DDR2 SDRAM modules use internally configured 4-bank or 8-

bank (512Mb, 1Gb) DDR2 SDRAM devices.

DDR2 SDRAM modules use double data rate architecture to achieve high-speed opera-

tion. The double data rate architecture is essentially a 4n-prefetch architecture with an

interface designed to transfer two data words per clock cycle at the I/O pins. A single

read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bit-

wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding

n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.

A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for

use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM

device during READs and by the memory controller during WRITEs. DQS is edge-

aligned with data for READs and center-aligned with data for WRITEs.

DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of

CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.

Commands (address and control signals) are registered at every positive edge of CK.

Input data is registered on both edges of DQS, and output data is referenced to both

edges of DQS, as well as to both edges of CK.

DDR2 SDRAM modules operate in registered mode, where the command/address input

signals are latched in the registers on the rising clock edge and sent to the DDR2 SDRAM

devices on the following rising clock edge (data access is delayed by one clock cycle). A

phase-lock loop (PLL) on the module receives and redrives the differential clock signals

(CK, CK#) to the DDR2 SDRAM devices. The registers and PLL minimize system and

clock loading. PLL clock timing is defined by JEDEC specifications and ensured by use of

the JEDEC clock reference board. Registered mode will add one clock cycle to CL.

Serial Presence-Detect Operation

DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is

implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256

bytes. The first 128 bytes can be programmed by Micron to identify the module type and

various SDRAM organizations and timing parameters. The remaining 128 bytes of

storage are available for use by the customer. System READ/WRITE operations between

the master (system logic) and the slave EEPROM device occur via a standard I

C bus

using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which

provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to V

SS on the

module, permanently disabling hardware write protect.

PDF: 09005aef818e3fc8/Source: 09005aef818e3fdb Micron Technology, Inc., reserves the right to change products or specifications without notice.

HTF36C256_512x72.fm - Rev. C 1/07 EN

2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM

Electrical Specifications

Stresses greater than those listed in Table 7 may cause permanent damage to the device.

This is a stress rating only, and functional operation of the device at these, or any other

conditions above those indicated in each device’s data sheet, is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect reliability.

Notes: 1. Refresh rate is required to double when T

exceeds 85°C.

2. For further information, refer to technical note TN-00-08: Thermal Applications, available

on Micron’s Web site.

Input Capacitance

Micron encourages designers to simulate the performance of the module to achieve

optimum values. Simulations are significantly more accurate and realistic than a gross

estimation of module capacitance when inductance and delay parameters associated

with trace lengths are used in simulations. JEDEC modules are currently designed using

simulations to close timing budgets.

Component Timing and Operating Conditions

Recommended AC operating conditions are given in the DDR2 component data sheets.

Component specifications are available on Micron’s Web site: www.micron.com. Module

speed grades correlate with component speed grades as shown in Table 8.

Table 7: Absolute Maximum Ratings

Symbol Parameter Min Max Units

VDD/VDDQ

VDD/VDDQ supply voltage relative to VSS

–0.50 2.3 V

IN, VOUT

Voltage on any pin relative to VSS

–0.5 2.3 V

Input leakage current; Any input 0V ≤ VIN ≤ VDD;

REF input 0V ≤ VIN ≤ 0.95V; (All other pins not

under test = 0V)

Command/Address

RAS#, CAS#, WE# S#,

CKE, ODT, BA

–10 10

µA

CK, CK#

–250 250

Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQs

and ODT are disabled

DQ, DQS, DQS#

–10 10 µA

IVREF

VREF leakage current; VREF = Valid VREF level

–72 72 µA

DDR2 SDRAM device operating temperature

Commercial

0+85°C

Table 8: Module and Component Speed Grade Table

Module Speed Grade Component Speed Grade

-80E -25E

-800 -25

-667 -3

-53E -37E

-40E -5E

PDF: 09005aef818e3fc8/Source: 09005aef818e3fdb Micron Technology, Inc., reserves the right to change products or specifications without notice.

HTF36C256_512x72.fm - Rev. C 1/07 EN

2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM

Electrical Specifications

IDD Specifications

Notes: 1. Value calculated as one module rank in this operating condition, all other module ranks in

DD2P (CKE LOW) mode.

2. Value calculated reflects all module ranks in this operating condition.

Table 9: DDR2 IDD Specifications and Conditions – 2GB

Values shown for MT47H128M4 DDR2 SDRAM only and are computed from values specified in the

512Mb (128 Meg x 4) component data sheet

Parameter/Condition Symbol

-80E

-800 -667 -53E -40E Units

Operating one bank active-precharge current:

CK =

CK (IDD),

RC =

RC (IDD),

RAS =

RAS MIN (IDD); CKE is HIGH, S# is HIGH between valid

commands; Address bus inputs are switching; Data bus inputs are switching

DD0

1,926 1,746 1,566 1,566 mA

Operating one bank active-read-precharge current: I

OUT = 0mA;

BL = 4, CL = CL (IDD), AL = 0;

CK =

CK (IDD),

RC =

RC (IDD),

RAS =

RAS MIN

DD),

RCD =

RCD (IDD); CKE is HIGH, S# is HIGH between valid commands;

Address bus inputs are switching; Data pattern is same as IDD4W

DD1

2,196 2,016 1,836 1,746 mA

Precharge power-down current: All device banks idle;

CK =

CK (IDD);

CKE is LOW; Other control and address bus inputs are stable; Data bus

inputs are floating

DD2P

252 252 252 252 mA

Precharge quiet standby current: All device banks idle;

CK =

CK (IDD);

CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;

Data bus inputs are floating

IDD2Q

1,800 1,620 1,440 1,260 mA

Precharge standby current: All device banks idle;

CK =

CK (IDD); CKE is

HIGH, S# is HIGH; Other control and address bus inputs are switching; Data

bus inputs are switching

IDD2N

1,980 1,800 1,620 1,440 mA

Active power-down current: All device banks open;

CK =

CK (IDD); CKE is LOW; Other control and address bus

inputs are stable; Data bus inputs are floating

Fast PDN exit

MR[12] = 0

DD3P

1,440 1,260 1,080 900 mA

Slow PDN exit

MR[12] = 1

432 432 432 432 mA

Active standby current: All device banks open;

CK =

CK (IDD),

RAS =

RAS MAX (IDD),

RP =

RP (IDD); CKE is HIGH, S# is HIGH between

valid commands; Other control and address bus inputs are switching; Data

bus inputs are switching

DD3N

2,520 2,340 1,980 1,620 mA

Operating burst write current: All device banks open; Continuous burst

writes; BL = 4, CL = CL (I

DD), AL = 0;

CK =

CK (IDD),

RAS =

RAS MAX (IDD),

RP =

RP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address

bus inputs are switching; Data bus inputs are switching

DD4W

3,636 3,186 2,646 2,196 mA

Operating burst read current: All device banks open; Continuous burst

reads, I

OUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;

CK =

CK (IDD),

RAS =

RAS

MAX (I

DD),

RP =

RP (IDD); CKE is HIGH, S# is HIGH between valid

commands; Address bus inputs are switching; Data bus inputs are switching

DD4R

3,816 3,366 2,736 2,196 mA

Burst refresh current:

CK =

CK (IDD); REFRESH command at every

RFC

(IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other

control and address bus inputs are switching; Data bus inputs are switching

DD5

8,280 6,480 6,120 5,940 mA

Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and

address bus inputs are floating; Data bus inputs are floating

DD6

252 252 252 252 mA

Operating bank interleave read current: All device banks interleaving

reads, I

OUT = 0mA; BL = 4, CL = CL (IDD), AL =

RCD (IDD) - 1 ×

CK (IDD);

CK =

CK (IDD),

RC =

RC (IDD),

RRD =

RRD (IDD),

RCD =

RCD (IDD); CKE is

HIGH, S# is HIGH between valid commands; Address bus inputs are stable

during DESELECTs; Data bus inputs are switching

DD7

5,526 4,446 4,176 4,086 mA

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

MT36HTF25672PY-667DZES

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Manufacturer:

Micron

Description:

MODULE DDR2 SDRAM 2GB 240RDIMM

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MT36HTF25672PY-667DZES

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