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HTF36C256_512x72.fm - Rev. C 1/07 EN
10 ©2005 Micron Technology, Inc. All rights reserved.
2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
Electrical Specifications
Notes: 1. Value calculated as one module rank in this operating condition, all other module ranks in
I
DD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.
Table 10: DDR2 IDD Specifications and Conditions – 4GB
Values shown for MT47H256M4 DDR2 SDRAM only and are computed from values specified in the
1Gb (256 Meg x 4) component data sheet
Parameter/Condition Symbol
-80E
-800
-667 -53E -40E Units
Operating one bank active-precharge current:
t
CK =
t
CK (IDD),
t
RC =
t
RC (IDD),
t
RAS =
t
RAS MIN (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
I
DD0
1
1,746 1,656 1,386 1,386 mA
Operating one bank active-read-precharge current: I
OUT = 0mA;
BL = 4, CL = CL (IDD), AL = 0;
t
CK =
t
CK (IDD),
t
RC =
t
RC (IDD),
t
RAS =
t
RAS MIN
(I
DD),
t
RCD =
t
RCD (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data pattern is same as IDD4W
I
DD1
1
2,106 1,926 1,836 1,746 mA
Precharge power-down current: All device banks idle;
t
CK =
t
CK (IDD);
CKE is LOW; Other control and address bus inputs are stable; Data bus
inputs are floating
I
DD2P
2
252 252 252 252 mA
Precharge quiet standby current: All device banks idle;
t
CK =
t
CK (IDD);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
IDD2Q
2
1,800 1,440 1,440 1,260 mA
Precharge standby current: All device banks idle;
t
CK =
t
CK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
IDD2N
2
1,800 1,440 1,440 1,260 mA
Active power-down current: All device banks open;
t
CK =
t
CK (IDD); CKE is LOW; Other control and address
bus inputs are stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0
I
DD3P
2
1,440 1,080 1,080 1,080 mA
Slow PDN exit
MR[12] = 1
360 360 360 360 mA
Active standby current: All device banks open;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS MAX (IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between
valid commands; Other control and address bus inputs are switching; Data
bus inputs are switching
I
DD3N
2
2,160 1,980 1,620 1,440 mA
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
DD), AL = 0;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS MAX (IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data bus inputs are switching
I
DD4W
1
3,006 2,556 2,376 2,016 mA
Operating burst read current: All device banks open; Continuous burst
reads, I
OUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS
MAX (I
DD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
I
DD4R
1
3,006 2,556 2,376 2,016 mA
Burst refresh current:
t
CK =
t
CK (IDD); REFRESH command at every
t
RFC
(I
DD) interval; CKE is HIGH, S# is HIGH between valid commands; Other
control and address bus inputs are switching; Data bus inputs are switching
I
DD5
2
8,460 7,740 7,560 7,380 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
I
DD6
2
252 252 252 252 mA
Operating bank interleave read current: All device banks interleaving
reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL =
t
RCD (IDD) - 1 ×
t
CK (IDD);
t
CK =
t
CK (IDD),
t
RC =
t
RC (IDD),
t
RRD =
t
RRD (IDD),
t
RCD =
t
RCD (IDD); CKE is
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during DESELECTs; Data bus inputs are switching
I
DD7
1
6,156 5,166 4,986 4,806 mA
