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MT5LSDT872AG-133G1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
32MB, 64MB, 128MB (x72, SR)
168-PIN SDRAM UDIMM
32, 64, 128MB x 64 SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD5C4_8_16x72AG.fm - Rev. C 6/04 EN
10 ©2004 Micron Technology, Inc. All rights reserved.
Operating Mode
The normal operating mode is selected by setting
M7 and M8 to zero; the other combinations of values
for M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
READ and WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with
future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-
M2 applies to both READ and WRITE bursts; when M9
= 1, the programmed burst length applies to READ
bursts, but write accesses are single-location (non-
burst) accesses.
Table 8: CAS Latency Table
SPEED
ALLOWABLE OPERATING CLOCK
FREQUENCY (MHz)
CAS LATENCY = 2 CAS LATENCY = 3
-13E ≤ 133 ≤ 143
-133 ≤ 100 ≤ 133
-10E ≤ 100 N/A
32MB, 64MB, 128MB (x72, SR)
168-PIN SDRAM UDIMM
32, 64, 128MB x 64 SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD5C4_8_16x72AG.fm - Rev. C 6/04 EN
11 ©2004 Micron Technology, Inc. All rights reserved.
Commands
Table 9, Commands and DQMB Operation Truth
Table, provides a general reference of available com-
mands. For a more detailed description of commands
and operations, refer to the 64Mb, 128Mb, or 256Mb
SDRAM component data sheet.
NOTE:
1. A0–A11 define the op-code written to the mode register, and for the 128MB module, A12 should be driven LOW.
2. A0–A11 (32MB and 64MB) or A0–A12 (128MB) provide device row address, and BA0, BA1 determine which device bank
is made active.
3. A0–A7 (32MB) or A0–A8 (64MB and 128MB) provide device column address; A10 HIGH enables the auto precharge fea-
ture (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which device bank is
being read from or written to.
4. A10 LOW: BA0, BA1 determine the device bank being precharged. A10 HIGH: All device banks precharged and BA0, BA1
are “Don’t Care.”
5. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
6. Internal refresh counter controls device row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
7. Activates or deactivates the DQ during WRITEs (zero-clock delay) and READs (two-clock delay).
Table 9: Commands and DQMB Operation Truth Table
CKE is HIGH for all commands shown except SELF REFRESH
NAME (FUNCTION) S# RAS# CAS# WE# DQMB ADDR DQS NOTES
COMMAND INHIBIT (NOP)
HXXX X X X
NO OPERATION (NOP)
LHHH X X X
ACTIVE (Select bank and activate row)
L L H H X Bank/Row X 2
READ (Select bank and column, and start READ
burst)
LHLH
L/H
8
Bank/Col X 3
WRITE (Select bank and column, and start WRITE
burst)
LHLL
L/H
8
Bank/Col Valid 3
BURST TERMINATE
LHHL X X Active
PRECHARGE (Deactivate row in bank or banks)
L L H L X Code X 4
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LLLH X X X 5, 6
LOAD MODE REGISTER
L L L L X Op-Code X 1
Write Enable/Output enable
–––– L – Active 7
Write Inhibit/Output High-Z
–––– H – High-Z 7
32MB, 64MB, 128MB (x72, SR)
168-PIN SDRAM UDIMM
32, 64, 128MB x 64 SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD5C4_8_16x72AG.fm - Rev. C 6/04 EN
12 ©2004 Micron Technology, Inc. All rights reserved.
Absolute Maximum Ratings
Stresses greater than those listed may cause perma-
nent damage to the device. This is a stress rating only,
and functional operation of the device at these or any
other conditions above those indicated in the opera-
tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Voltage on V
DD, VDDQ Supply
Relative to V
SS . . . . . . . . . . . . . . . . . . . .-1V to +4.6V
Voltage on Inputs, NC or I/O Pins
Relative to V
SS . . . . . . . . . . . . . . . . . . . .-1V to +4.6V
Operating Temperature
T
OPR
(Commercial - ambient) . . . . . .0°C to +65°C
T
OPR
(Industrial - ambient). . . . . . .-40°C to +85°C
Storage Temperature (plastic) . . . . . .-55°C to +150°C
Table 10: DC Electrical Characteristics and Operating Conditions
Notes: 1, 5, 6; notes appear following the parameter tables; VDD, VDDQ = +3.3V ±0.3V
PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES
SUPPLY VOLTAGE
V
DD, VDDQ3 3.6 V
INPUT HIGH VOLTAGE: Logic 1; All inputs
V
IH 2VDD + 0.3 V22
INPUT LOW VOLTAGE: Logic 0; All inputs
V
IL -0.3 0.8 V 22
INPUT LEAKAGE CURRENT: Any input 0V ≤ V
IN
≤ V
DD (All other pins not under
test = 0V)
Command/
Address, CKE
I
I
-25 25
µA 33
CK, S0#
-15 15
CK2, S2#
-10 10
DQMB
-5 5
OUTPUT LEAKAGE CURRENT: DQs are disabled;
0V ≤ V
OUT ≤ VDDQ
DQ
IOZ -5 5 µA 33
OUTPUT LEVELS: Output High Voltage (I
OUT = -
4mA)
V
OH 2.4 – V
Output Low Voltage (IOUT = 4mA)
V
OL –0.4V
Table 11: IDD Specifications and Conditions – 32MB
Notes: 1, 5, 6, 11, 13; notes appear following the parameter tables; VDD, VDDQ = +3.3V ±0.3V; DRAM components only
MAX
PARAMETER/CONDITION SYMBOL -13E -133 -10E UNITS NOTES
OPERATING CURRENT: Active Mode; Burst = 2; READ or
WRITE;
t
RC =
t
RC (MIN)
I
DD1 625 575 475 mA 3, 18, 19,
29
STANDBY CURRENT: Power-Down Mode; All device banks
idle; CKE = LOW
I
DD2 10 10 10 mA 29
STANDBY CURRENT: Active Mode; CKE = HIGH; CS# = HIGH;
All device banks active after
t
RCD met; No accesses in
progress
I
DD3 225 225 175 mA 3, 12, 19,
29
OPERATING CURRENT: Burst Mode; Continuous burst; READ
or WRITE; All device banks active
I
DD4 750 700 600 mA 3, 18, 19,
29
AUTO REFRESH CURRENT
CS# = HIGH; CKE = HIGH
t
RFC =
t
RFC (MIN)
I
DD5 1,150 1,050 950 mA 3, 12, 18,
19, 29, 30
t
RFC = 15.62µs
I
DD6 15 15 15 mA
SELF REFRESH CURRENT: CKE ≤ 0.2V
I
DD7 555mA 4
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

MT5LSDT872AG-133G1

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Buy MT5LSDT872AG-133G1
Manufacturer:
Micron
Description:
MODULE SDRAM 64MB 168UDIMM
Lifecycle:
New from this manufacturer.
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