32MB, 64MB, 128MB (x72, SR)
168-PIN SDRAM UDIMM
32, 64, 128MB x 64 SDRAM DIMM Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD5C4_8_16x72AG.fm - Rev. C 6/04 EN
7 ©2004 Micron Technology, Inc. All rights reserved.
General Description
The Micron
®
MT5LSDT472A, MT5LSDT872A(I), and
MT5LSDT1672A(I) are a high-speed CMOS, dynamic
random-access, 32MB, 64MB, and 128MB memory
modules organized in a x72, ECC configuration. ECC
functions to detect and correct one-bit memory errors.
These module use SDRAM devices which are internally
configured as quad-bank DRAMs with a synchronous
interface (all signals are registered on the positive edge
of the clock signals CK0, CK2).
Read and write accesses to the SDRAM module are
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed (BA0, BA1 select the device bank, A0–A11 for
32MB and 64MB; A0–A12 for 128MB select the device
row). The address bits registered coincident with the
READ or WRITE command (A0–A7 32MB; A0–A8 64MB
and 128MB) are used to select the starting device col-
umn location for the burst access.
These modules provide for programmable READ or
WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence. These modules use an internal pipelined
architecture to achieve high-speed operation. This
architecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one device
bank while accessing one of the other three device
banks will hide the PRECHARGE cycles and provide
seamless, high-speed, random access operation.
These modules are designed to operate in 3.3V, low-
power memory systems. An auto refresh mode is pro-
vided, along with a power-saving, power-down mode.
All inputs, outputs, and clocks are LVTTL-compatible.
SDRAM modules offer substantial advances in
DRAM operating performance, including the ability to
synchronously burst data at a high data rate with auto-
matic column-address generation, the ability to inter-
leave between internal banks in order to hide
precharge time, and the capability to randomly change
column addresses on each clock cycle during a burst
access. For more information regarding SDRAM opera-
tion, refer to the 64Mb, 128Mb, or 256Mb SDRAM
component data sheets.
Serial Presence-Detect Operation
These modules incorporate serial presence-detect
(SPD). The SPD function is implemented using a
2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be pro-
grammed by Micron to identify the module type and
various SDRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for
use by the customer. System READ/WRITE operations
between the master (system logic) and the slave
EEPROM device (DIMM) occur via a standard IIC bus
using the DIMM’s SCL (clock) and SDA (data) signals.
Write protect (WP) is tied to ground on the module,
permanently disabling hardware write protect.
Initialization
SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other
than those specified may result in undefined opera-
tion. Once power is applied to V
DD and VDDQ (simulta-
neously) and the clock is stable (stable clock is defined
as a signal cycling within timing constraints specified
for the clock pin), the SDRAM requires a 100µs delay
prior to issuing any command other than a COM-
MAND INHIBIT or NOP. Starting at some point during
this 100µs period and continuing at least through the
end of this period, COMMAND INHIBIT or NOP com-
mands should be applied.
Once the 100µs delay has been satisfied with at least
one COMMAND INHIBIT or NOP command having
been applied, a PRECHARGE command should be
applied. All device banks must then be precharged,
thereby placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles
must be performed. After the AUTO REFRESH cycles
are complete, the SDRAM is ready for mode register
programming. Because the mode register will power
up in an unknown state, it should be loaded prior to
applying any operational command.
Mode Register Definition
The mode register is used to define the specific
mode of operation of the SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency, an operating mode, and a write burst
mode, as shown in the Mode Register Definition Dia-
gram. The mode register is programmed via the LOAD
MODE REGISTER command and will retain the stored
information until it is programmed again or the device
loses power.
