XC95288XL-6BGG256C

DS055 (v2.1 April 3, 2007 www.xilinx.com 1
Product Specification 1-800-255-7778
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Features
6 ns pin-to-pin logic delays
System frequency up to 208 MHz
288 macrocells with 6,400 usable gates
Available in small footprint packages
- 144-pin TQFP (117 user I/O pins)
- 208-pin PQFP (168 user I/O pins)
- 256-pin BGA (192 user I/O pins)
- 256-pin FBGA (192 user I/O pins)
- 280-pin CSP (192 user I/O pins)
- Pb-free available for all packages
Optimized for high-performance 3.3V systems
- Low power operation
- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS
Fast FLASH™ technology
Advanced system features
- In-system programmable
- Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin with local
inversion
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
- Endurance exceeding 10,000 program/erase
cycles
- 20 year data retention
- ESD protection exceeding 2,000V
Pin-compatible with 5V-core XC95288 device in the
208-pin HQFP package
WARNING: Programming temperature range of
T
A
= 0° C to +70° C
Description
The XC95288XL is a 3.3V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of 16
54V18 Function Blocks, providing 6,400 usable gates with
propagation delays of 6 ns. See Figure 2 for architecture
overview.
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of I
CC
, the following equation may be
used:
I
CC
(mA) = MC
HS
(0.175*PT
HS
+ 0.345) + MC
LP
(0.052*PT
LP
+ 0.272) + 0.04 * MC
TOG
(MC
HS
+MC
LP
)* f
where:
MC
HS
= # macrocells in high-speed configuration
PT
HS
= average number of high-speed product terms
per macrocell
MC
LP
= # macrocells in low power configuration
PT
LP
= average number of low power product terms per
macrocell
f = maximum clock frequency
MCTOG = average % of flip-flops toggling per clock
(~12%)
This calculation was derived from laboratory measurements
of an XC9500XL part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual I
CC
value varies with the design application and should be veri-
fied during normal system operation. Figure 1 shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
0
XC95288XL High Performance
CPLD
DS055 (v2.1 April 3, 2007
05
Product Specification
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XC95288XL High Performance CPLD
2 www.xilinx.com DS055 (v2.1 April 3, 2007
1-800-255-7778 Product Specification
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application note XAPP114, “Understanding XC9500XL
CPLD Power.”
Figure 1: Typical I
CC
vs. Frequency for XC95288XL
Clock Frequency (MHz)
Typical I
CC
(mA)
100 200 250
DS055_01_121501
200
250
300
350
400
450
500
550
50
50 150
150
100
0
94 MHz
HighP
e
rformanc
e
208 MHz
L
o
wPo
wer
XC95288XL High Performance CPLD
DS055 (v2.1 April 3, 2007 www.xilinx.com 3
Product Specification 1-800-255-7778
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Figure 2: XC95288XL Architecture
Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.
In-System Programming Controller
JTAG
Controller
I/O
Blocks
Function
Block 1
Macrocells
1 to 18
Macrocells
1 to 18
JTAG Port
3
54
I/O/GTS
I/O/GSR
I/O/GCK
I/O
I/O
I/O
I/O
4
1
I/O
I/O
I/O
I/O
3
DS055_02_101300
1
Function
Block 2
54
18
18
Function
Block 3
Macrocells
1 to 18
Macrocells
1 to 18
54
Function
Block 16
54
18
18
Function
Block 4
Macrocells
1 to 18
54
18
Fast CONNECT II Switch Matrix

XC95288XL-6BGG256C

Mfr. #:
XC95288XL-6BGG256C
Manufacturer:
Xilinx
Description:
CPLD - Complex Programmable Logic Devices 3.3V 288-mc CPLD
Lifecycle:
New from this manufacturer.
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