MT9HTF12872FZ-80EH1N8

General Description
Micron’s FBDIMM devices adhere to the currently proposed industry specifications for
FBDIMMs. The following specifications contain detailed information on FBDIMM de-
sign, interfaces, and theory of operation and are listed here for the system designers’
convenience. Refer to the JEDEC Web site for available specifications.
FBDIMM Design Specification – pending JEDEC approval
FBDIMM: Architecture and Protocol – JESD206
FBDIMM: Advanced Memory Buffer (AMB) – JESD82-20
Design for Test, Design for Validation (DFx) Specification
Serial Presence-Detect (SPD) for Fully Buffered DIMM – JEDEC Standard No. 21-C,
page 4.1.2.7-1
This DDR2 SDRAM module is a high-bandwidth, large-capacity channel solution that
has a narrow host interface. FBDIMM devices use DDR2 SDRAM devices isolated from
the channel behind an AMB on the FBDIMM. Memory device capacity remains high,
and total memory capacity scales with DDR2 SDRAM bit density.
As shown in the System Block Diagram, the FBDIMM channel provides a communica-
tion path from a host controller to an array of DDR2 SDRAM devices, with the DDR2
SDRAM devices buffered behind an AMB device. The physical isolation of the DDR2
SDRAM devices from the channel enhances the communication path and significantly
increases the reliability and availability of the memory subsystem.
Advanced Memory Buffer
The AMB isolates the DDR2 SDRAM devices from the channel. This single-chip AMB
component, located in the center of each FBDIMM, acts as a repeater and buffer for all
signals and commands exchanged between the host controller and DDR2 SDRAM devi-
ces, including data input and output. The AMB communicates with the host controller
and adjacent FBDIMMs on a system board using an industry-standard, high-speed, dif-
ferential, 1.5V, point-to-point interface. The AMB also enables buffering of memory traf-
fic to support large memory capacities. Refer to the JEDEC JESD82-20 specification for
further information.
1GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM
General Description
PDF: 09005aef83de8266
htf9c128x72fz.pdf - Rev. B 4/14 EN
7
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other condi-
tions outside those indicated in the device data sheet is not implied. Exposure to abso-
lute maximum rating conditions for extended periods may adversely affect reliability.
Table 6: Absolute Maximum Ratings
Parameter Symbol Min Max Units Notes
Voltage on any pin relative to V
SS
V
IN
, V
OUT
–0.3 +1.75 V 1
Voltage on V
CC
pin relative to V
SS
V
CC
–0.3 +1.75 V
Voltage on V
DD
pin relative to V
SS
V
DD
–0.5 +2.3 V
Voltage on V
TT
pin relative to V
SS
V
TT
–0.5 +2.3 V
DDR2 SDRAM device operating case temperature T
C
0 +95 °C 2, 3
AMB device operating temperature 0 +110 °C
Notes:
1. V
IN
should not be greater than V
CC
.
2. T
C
is specified at 95°C only when using 2X refresh timing (
t
REFI = 7.8µs at or below 85°C;
t
REFI = 3.9µs above 85°C); refer to the DDR2 SDRAM component data sheet.
3. See applicable DDR2 SDRAM component data sheet for
t
REFI and extended mode regis-
ter settings. The
t
REFI parameter is used to specify the doubled refresh interval necessa-
ry to sustain <85°C operation.
Table 7: Input DC Voltage and Operating Conditions
Parameter Symbol Min Nom Max Units Notes
AMB supply voltage V
CC
1.46 1.5 1.54 V
DDR2 SDRAM supply voltage V
DD
1.7 1.8 1.9 V
Termination voltage V
TT
0.48 × V
DD
0.5 × V
DD
0.52 × V
DD
V
EEPROM supply voltage V
DDSPD
3 3.3 3.6 V 1
SPD input high (logic 1) voltage V
IH(DC)
2.1 V
DDSPD
V 2
SPD input low (logic 0) voltage V
IL(DC)
0.8 V 2
RESET input high (logic 1) voltage V
IH(DC)
1 V 3
RESET input low (logic 0) voltage V
IL(DC)
0.5 V 2
Leakage current (RESET) l
L
–90 +90 µA 3
Leakage current (link) l
L
–5 +5 µA 4
Notes:
1. Applies to AMB and SPD.
2. Applies to serial memory buffer (SMB) and SPD bus signals.
3. Applies to AMB CMOS signal RESET#.
4. For all other AMB-related DC parameters, please refer to the high-speed differential link
interface specification.
1GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM
Electrical Specifications
PDF: 09005aef83de8266
htf9c128x72fz.pdf - Rev. B 4/14 EN
8
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Table 8: Clock Rates
FBDIMM Link Data Rate Reference Clock DRAM Clock DRAM Data Rate
3.2 Gb/s 133 MHz 266 MHz 533 Mb/s
4.0 Gb/s 167 MHz 333 MHz 666 Mb/s
4.8 Gb/s 200 MHz 400 MHz 800 Mb/s
Note:
1. DDR2 components may exceed the listed module speed grades; module may not be
available in all listed speed grades
I
DD
Conditions and Specifications
Table 9: I
DD
Conditions
Symbol Condition
I
DD_IDLE_0
Idle current, single, or last DIMM: L0 state; Idle (0% bandwidth); Primary channel ena-
bled; Secondary channel disabled; CKE HIGH; Command and address lines stable; DDR2
SDRAM clock active
I
DD_IDLE_1
Idle current, first DIMM: L0 state; Idle (0% bandwidth); Primary and secondary channels
enabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active
I
DD_ACTIVE_1
Active power: L0 state; 50% DRAM bandwidth; 67% READ; 33% WRITE; Primary and sec-
ondary channels enabled; DDR2 SDRAM clock active; CKE HIGH
I
DD_ACTIVE_2
Active power, data pass through: L0 state; 50% DRAM bandwidth to downstream DIMM;
67% READ; 33% WRITE; Primary and secondary channels enabled; DDR2 SDRAM clock active;
CKE HIGH; Command and address lines stable
I
DD_TRAINING
Training: Primary and secondary channels enabled; 100% toggle on all channel lanes;
DRAMs idle; 0% bandwidth; CKE HIGH; Command and address lines stable; DDR2 SDRAM
clock active
I
DD_IBIST
IBIST over all IBIST modes: DRAM idle (0% bandwidth); Primary channel enabled; Secon-
dary channel enabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock ac-
tive
I
DD_EI
Electrical idle: DRAM idle (0% bandwidth); Primary channel disabled; Secondary channel
disabled; CKE LOW; Command and address lines floated; DDR2 SDRAM clock active; ODT and
CKE driven LOW
Note:
1. Actual test conditions may vary from published JEDEC test conditions.
Table 10: I
DD
Specifications – 1GB DDR2-667 (Die revision H)
Symbol I
DD_IDLE_0
I
DD_IDLE_1
I
DD_ACTIVE_1
I
DD_ACTIVE_2
I
DD_TRAINING
I
DD_IBIST
I
DD_EI
Units
I
CC
2600 3400 3900 3700 4000 4500 2500 mA
I
DD
916 916 1945 916 916 916 263 mA
Total power 5.8 7.0 9.8 7.5 8.0 8.8 4.4 W
1GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM
I
DD
Conditions and Specifications
PDF: 09005aef83de8266
htf9c128x72fz.pdf - Rev. B 4/14 EN
9
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.

MT9HTF12872FZ-80EH1N8

Mfr. #:
Manufacturer:
Micron
Description:
MODULE DDR2 SDRAM 1GB 240FBDIMM
Lifecycle:
New from this manufacturer.
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