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XC18V512PC20C

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
XC18V00 Series In-System-Programmable Configuration PROMs
DS026 (v5.2) January 11, 2008 www.xilinx.com
Product Specification 10
R
X-Ref Target - Figure 5
Figure 5: Master Serial Mode
Xilinx FPGA
Master Serial
DIN
CCLK
DONE
INIT_B (INIT)
PROG_B (PROGRAM)
TDI
TMS
TCK
GND
MODE PINS
(1)
DOUT
TDO
V
CCO
V
CCINT
DOUT
CCLK
DONE
INIT_B (INIT)
PROG_B (PROGRAM)
DIN
CCLK
DONE
INIT_B (INIT)
PROG_B (PROGRAM)
4.7 kΩ
4.7 kΩ
(1)
V
CCO
(2)
...OPTIONAL
Daisy-chained
Slave FPGAs
with different
configurations
...OPTIONAL
Slave FPGAs
with identical
configurations
TDI
TMS
TCK
TDO
Notes:
1 For MODE pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet or user guide.
2 For compatible voltages, refer to the appropriate data sheet.
XC18V00
PROM
V
CCINT
V
CCO
(2)
TDI
TMS
TCK
GND
D0
CLK
CE
CEO
OE/RESET
CF
TDO
ds026_18_20051007
XC18V00 Series In-System-Programmable Configuration PROMs
DS026 (v5.2) January 11, 2008 www.xilinx.com
Product Specification 11
R
X-Ref Target - Figure 6
Figure 6: Master/Slave SelectMAP Mode or Slave Parallel Mode
XC18V00
PROM
V
CCINT
V
CCO
(2)
GND
D[0:7]
CLK
CE
CEO
OE/RESET
CF
TDO
Xilinx FPGA
SelectMAP or
Slave-Parallel
D[0:7]
CCLK
DONE
INIT_B (INIT)
PROG_B (PROGRAM)
TDI
TMS
TCK
GND
MODE PINS
(1)
RDWR_B
CS_B
TDO
V
CCO
V
CCINT
D[0:7]
CCLK
DONE
INIT_B (INIT)
PROG_B (PROGRAM)
4.7 kΩ
4.7 kΩ
(1)
V
CCO
(2)
...OPTIONAL
Slave FPGAs
with identical
configurations
Notes:
1 For MODE pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet or user guide.
2 For compatible voltages, refer to the appropriate data sheet.
3 External oscillator required for Virtex/Virtex-E SelectMAP, for Virtex-II/Virtex-II Pro Slave SelectMAP, and for
Spartan-II/Spartan-IIE Slave-Parallel modes.
DS026_19_111207
External
Oscillator
(3)
TDI
TMS
TCK
TDO
8
XC18V00 Series In-System-Programmable Configuration PROMs
DS026 (v5.2) January 11, 2008 www.xilinx.com
Product Specification 12
R
X-Ref Target - Figure 7
Figure 7: Configuring Multiple Devices in Master/Slave Serial Mode
XC18V00
PROM
First
PROM
(PROM 0)
V
CCINT
V
CCO
(2)
TDI
TMS
TCK
D0
CLK
CE
CEO
OE/RESET
CF
TDO
Xilinx FPGA
Master Serial
DIN
CCLK
DONE
INIT_B (INIT)
PROG_B (PROGRAM)
TDI
TMS
TCK
MODE PINS
(1)
DOUT
TDO
4.7 kΩ
4.7 kΩ
(1)
V
CCO
(2)
TDI
TMS
TCK
TDO
Notes:
1 For MODE pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet or user guide.
2 For compatible voltages, refer to the appropriate data sheet.
Xilinx FPGA
Slave Serial
DIN
CCLK
DONE
INIT_B (INIT)
PROG_B (PROGRAM)
TDI
TMS
TCK
XC18V00
PROM
Cascaded
PROM
(PROM 1)
V
CCINT
V
CCO
(2)
TDI
TMS
TCK
D0
CLK
CE
CEO
OE/RESET
CF
TDO
V
CCO
V
CCINT
MODE PINS
(1)
TDO
ds026_16_20051007
GND
GNDGND
GND
V
CCO
V
CCINT
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

XC18V512PC20C

Mfr. #:
Buy XC18V512PC20C
Manufacturer:
Xilinx
Description:
FPGA - Configuration Memory
Lifecycle:
New from this manufacturer.
Delivery:
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