© 2009 Microchip Technology Inc. DS21828F-page 13
25AA320A/25LC320A
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardless of
the CS
input signal. If CS is brought high during a
program cycle, the device will go into Standby mode as
soon as the programming cycle is complete. When the
device is deselected, SO goes to the high-impedance
state, allowing multiple parts to share the same SPI
bus. A low-to-high transition on CS
after a valid write
sequence initiates an internal write cycle. After power-
up, a low level on CS is required prior to any sequence
being initiated.
3.2 Serial Output (SO)
The SO pin is used to transfer data out of the
25XX320A. During a read cycle, data is shifted out on
this pin after the falling edge of the serial clock.
3.3 Write-Protect (WP)
This pin is used in conjunction with the WPEN bit in the
STATUS register to prohibit writes to the nonvolatile
bits in the STATUS register. When WP
is low and
WPEN is high, writing to the nonvolatile bits in the STA-
TUS register is disabled. All other operations function
normally. When WP
is high, all functions, including
writes to the nonvolatile bits in the STATUS register
operate normally. If the WPEN bit is set, WP
low during
a STATUS register write sequence will disable writing
to the STATUS register. If an internal write cycle has
already begun, WP
going low will have no effect on the
write.
The WP
pin function is blocked when the WPEN bit in
the STATUS register is low. This allows the user to
install the 25XX320A in a system with WP pin
grounded and still be able to write to the STATUS
register. The WP pin functions will be enabled when the
WPEN bit is set high.
3.4 Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
3.5 Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the 25XX320A. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
3.6 Hold (HOLD)
The HOLD pin is used to suspend transmission to the
25XX320A while in the middle of a serial sequence
without having to retransmit the entire sequence again.
It must be held high any time this function is not being
used. Once the device is selected and a serial
sequence is underway, the HOLD
pin may be pulled
low to pause further serial communication without
resetting the serial sequence. The HOLD
pin must be
brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high-to-
low transition. The 25XX320A must remain selected
during this sequence. The SI, SCK and SO pins are in
a high-impedance state during the time the device is
paused and transitions on these pins will be ignored. To
resume serial communication, HOLD
must be brought
high while the SCK pin is low, otherwise serial
communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.
Name Pin
Number
X-Rotated
Pin
Number
Function
CS
1 3 Chip Select Input
SO 2 4 Serial Data Output
WP
3 5 Write-Protect Pin
VSS 4 6 Ground
SI 5 7 Serial Data Input
SCK 6 8 Serial Clock Input
HOLD
7 1 Hold Input
V
CC 8 2 Supply Voltage
Note: The exposed pad on the TDFN package
can be connected to V
SS or left floating.
25AA320A/25LC320A
DS21828F-page 14 © 2009 Microchip Technology Inc.
4.0 PACKAGING INFORMATION
4.1 Package Marking Information
8-Lead MSOP (150 mil)
Example:
XXXXXT
YWWNNN
5LBAI
3281L7
T/XXXNNN
XXXXXXXX
YYWW
8-Lead PDIP
8-Lead SOIC
XXXXYYWW
XXXXXXXT
NNN
XXXX
TYWW
8-Lead TSSOP
NNN
I/P 1L7
25LC320A
0328
Example:
Example:
SN 0728
25LC32AI
1L7
1L7
5LBA
I328
Example:
3
e
3
e
8-Lead 2x3 TDFN Example:
XXX
YWW
NN
C71
828
17
TSSOP 1st Line Marking
Device std mark
25AA320A 5ABA
25AA320AX ABAX
25LC320A 5LBA
25LC320AX LBAX
MSOP 1st Line Marking
Device std mark
25AA320A 5ABAT
25LC320A 5LBAT
TDFN 1st Line Marking
Device std mark
25AA320A-I C71
25LC320A-E C74
25LC320A-I C75
© 2009 Microchip Technology Inc. DS21828F-page 15
25AA320A/25LC320A
Note: Custom marking available.
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e

25LC320AX-I/ST

Mfr. #:
Manufacturer:
Microchip Technology
Description:
EEPROM 32K 4KX8 2.5V SER EE IND
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union