3
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II
TM
36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
PIN CONFIGURATIONS (CONTINUED)
PBGA: 1mm pitch, 13mm x 13mm (BB144, order code: BB)
TOP VIEW
ASYW WEN
WCLK
PAF
FF/IR
HF BM EF
RCLK
REN OE
Q35
SEN
IW
PRS LD MRS
FS0 FS1
ASYR
IP PFM
RT
Q34
D35
D34
D33 FWFT/SI OW V
CC VCC
BE PAE
RM Q32 Q3
3
D32 D31 D30 V
CC VCC GND GND VCC VCC Q29 Q30 Q31
D29
D26
D27 V
CC Q26 Q27
Q28
D28
D25 D24
Q23
Q24 Q25
D21 D22 D23 Q22 Q21 Q20
D18 D19 D20 V
CC Q19 Q18 Q17
D15 D16 D17 V
CC Q16 Q15 Q14
D12 D13 D14 D3 D0 V
CC VCC TDO Q2
Q13 Q12
Q11
D10 D6 D4
D1
TMS
TCK
Q0 Q3 Q5 Q10 Q9
D8
D7 D5
D2
TRST
TDI Q1 Q4 Q6 Q7 Q8
A1 BALL PAD CORNER
A
B
C
D
E
F
G
H
J
K
L
M
12 3 4 5 6 7 8 9 1011 12
4667 drw02b
GND GND GND GND
GND GND GND GND
VCC
GND GND GND GND
VCC
GND
GND V
CC VCC
GND GND GND GND
D11
D9
V
CC
VCC
VCC
VCC
VCC
WCLK when WEN is asserted. During Asynchronous operation only the WR
input is used to write data into the FIFO. Data is written on a rising edge of WR,
the WEN input should be tied to its active state, (LOW).
The output port can be selected as either a Synchronous (clocked) interface,
or Asynchronous interface. During Synchronous operation the output port is
controlled by a Read Clock (RCLK) input and Read Enable (REN) input. Data
is read from the FIFO on every rising edge of RCLK when REN is asserted.
During Asynchronous operation only the RD input is used to read data from the
FIFO. Data is read on a rising edge of RD, the REN input should be tied to its
active state, LOW. When Asynchronous operation is selected on the output port
the FIFO must be configured for Standard IDT mode, and the OE input used
to provide three-state control of the outputs, Qn.
The frequencies of both the RCLK and the WCLK signals may vary from 0
to fMAX with complete independence. There are no restrictions on the frequency
of the one clock input with respect to the other.
There are two possible timing modes of operation with these devices: IDT
Standard mode and First Word Fall Through (FWFT) mode.
In IDT Standard mode, the first word written to an empty FIFO will not appear
on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating REN and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines.
In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A REN does
not have to be asserted for accessing the first word. However, subsequent
