10
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II
TM
36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
AC ELECTRICAL CHARACTERISTICS
(1)
— ASYNCHRONOUS TIMING
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
Commercial Com’l & Ind’l
IDT72V3640L6 IDT72V3640L7-5
IDT72V3650L6 IDT72V3650L7-5
IDT72V3660L6 IDT72V3660L7-5
IDT72V3670L6 IDT72V3670L7-5
IDT72V3680L6 IDT72V3680L7-5
IDT72V3690L6 IDT72V3690L7-5
Symbol Parameter Min. Max. Min. Max. Unit
fA
(4)
Cycle Frequency (Asynchronous mode) 100 83 MHz
tAA
(4)
Data Access Time 0.6 8 0.6 10 ns
tCYC
(4)
Cycle Time 10 12 ns
tCYH
(4)
Cycle HIGH Time 4.5 5 ns
tCYL
(4)
Cycle LOW Time 4.5 5 ns
tRPE
(4)
Read Pulse after EF HIGH 8 10 ns
tFFA
(4)
Clock to Asynchronous FF —8 10ns
tEFA
(4)
Clock to Asynchronous EF —8 10ns
tPAFA
(4)
Clock to Asynchronous Programmable Almost-Full Flag 8 10 ns
tPAEA
(4)
Clock to Asynchronous Programmable Almost-Empty Flag 8 10 ns
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
4. Paramaeters apply to the PBGA package only.
11
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II
TM
36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
4667 drw04
330Ω
30pF*
510Ω
3.3V
D.U.T.
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
(1)
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load for t
CLK = 10ns, 15 ns See Figure 2a
Output Load for t
CLK = 6ns, 7.5ns See Figure 2b & 2c
AC TEST CONDITIONS
Figure 2b. AC Test Load
Figure 2c. Lumped Capacitive Load, Typical Derating
AC TEST LOADS - 6ns, 7.5ns Speed Grades
Figure 2a. Output Load
* Includes jig and scope capacitances.
AC TEST LOADS - 10ns, 15ns Speed Grades
NOTE:
1. For 166MHz and 133MHz operation input rise/fall times are 1.5ns.
4667 drw04a
50
Ω
1.5V
I/O
Z
0
= 50
Ω
4667 drw04b
6
5
4
3
2
1
20 30 50 80 100 200
Ca
p
acitance
(p
F
)
t
CD
(Typical, ns)
V
IH
OE
V
IL
t
OE &
t
OLZ
V
CC
2
V
CC
2
100mV
100mV
t
OHZ
100mV
100mV
Output
Normally
LOW
Output
Normally
HIGH
V
OL
V
OH
V
CC
2
V
CC
2
4667 drw04c
Output
Enable
Output
Disable
OUTPUT ENABLE & DISABLE TIMING
NOTE:
1. REN is HIGH.
12
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II
TM
36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
If the FIFO is full, the first read operation will cause FF to go HIGH.
Subsequent read operations will cause PAF and HF to go HIGH at the conditions
described in Table 3. If further read operations occur, without write operations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offset value. Continuing read operations will cause the FIFO to become empty.
When the last word has been read from the FIFO, the EF will go LOW inhibiting
further read operations. REN is ignored when the FIFO is empty.
When configured in IDT Standard mode, the EF and FF outputs are double
register-buffered outputs.
Relevant timing diagrams for IDT Standard mode can be found in Figure
7,8,11 and 13.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manner outlined in Table 4. To write data into to the FIFO, WEN must be LOW.
Data presented to the DATA IN lines will be clocked into the FIFO on subsequent
transitions of WCLK. After the first write is performed, the Output Ready (OR)
flag will go LOW. Subsequent writes will continue to fill up the FIFO. PAE will go
HIGH after n + 2 words have been loaded into the FIFO, where n is the empty
offset value. The default setting for these values are stated in the footnote of Table
2. This parameter is also user programmable. See section on Programmable
Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the HF would toggle to LOW once the 514th word
for the IDT72V3640, 1,026th word for the IDT72V3650, 2,050th word for the
IDT72V3660, 4,098th word for the IDT72V3670, 8,194th word for the
IDT72V3680, 16,386th word for the IDT72V3690, respectively was written into
the FIFO. Continuing to write data into the FIFO will cause the PAF to go LOW.
Again, if no reads are performed, the PAF will goLOW after (1,025-m) writes
for the IDT72V3640, (2,049-m) writes for the IDT72V3650, (4,097-m) writes
for the IDT72V3660 and (8,193-m) writes for the IDT72V3670, (16,385-m)
writes for the IDT72V3680 and (32,769-m) writes for the IDT72V3690, where
m is the full offset value. The default setting for these values are stated in the
footnote of Table 2.
When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further
write operations. If no reads are performed after a reset, IR will go HIGH after
D writes to the FIFO. D = 1,025 writes for the IDT72V3640, 2,049 writes for
the IDT72V3650, 4,097 writes for the IDT72V3660 and 8,193 writes for the
IDT72V3670,16,385 writes for the IDT72V3680 and 32,769 writes for the
IDT72V3690, respectively. Note that the additional word in FWFT mode is due
to the capacity of the memory plus output register.
If the FIFO is full, the first read operation will cause the IR flag to go LOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditions described in Table 4. If further read operations occur, without write
operations, the PAE will go LOW when there are n + 1 words in the FIFO, where
n is the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read from the FIFO, OR will go
HIGH inhibiting further read operations. REN is ignored when the FIFO is empty.
When configured in FWFT mode, the OR flag output is triple register-
buffered, and the IR flag output is double register-buffered.
Relevant timing diagrams for FWFT mode can be found in Figure 9, 10, 12,
and 14.
FUNCTIONAL DESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690 sup-
port two different timing modes of operation: IDT Standard mode or First Word
Fall Through (FWFT) mode. The selection of which mode will operate is
determined during Master Reset, by the state of the FWFT/SI input.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (EF) to indicate whether or
not there are any words present in the FIFO. It also uses the Full Flag function
(FF) to indicate whether or not the FIFO has any free space for writing. In IDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the data outputs (Qn). It also uses Input Ready (IR) to indicate
whether or not the FIFO has any free space for writing. In the FWFT mode,
the first word written to an empty FIFO goes directly to Q
n after three RCLK rising
edges, REN = LOW is not necessary. Subsequent words must be accessed
using the Read Enable (REN) and RCLK.
Various signals, both input and output signals operate differently depending
on which timing mode is in effect.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manner outlined in Table 3. To write data into to the FIFO, Write Enable (WEN)
must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (EF) will go HIGH. Subsequent writes will continue
to fill up the FIFO. The Programmable Almost-Empty flag (PAE) will go HIGH
after n + 1 words have been loaded into the FIFO, where n is the empty offset
value. The default setting for these values are stated in the footnote of Table 2.
This parameter is also user programmable. See section on Programmable Flag
Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full flag (HF) would toggle to LOW once
the 513rd word for IDT72V3640, 1,025th word for IDT72V3650, 2,049th word
for IDT72V3660, 4,097th word for IDT72V3670, 8,193th word for the
IDT72V3680 and 16,385th word for the IDT72V3690, respectively was written
into the FIFO. Continuing to write data into the FIFO will cause the Programmable
Almost-Full flag (PAF) to go LOW. Again, if no reads are performed, the PAF
will go LOW after (1,024-m) writes for the IDT72V3640, (2,048-m) writes for the
IDT72V3650, (4,096-m) writes for the IDT72V3660, (8,192-m) writes for the
IDT72V3670, (16,384-m) writes for the IDT72V3680 and (32,768-m) writes
for the IDT72V3690. The offset “m” is the full offset value. The default setting
for these values are stated in the footnote of Table 2. This parameter is also user
programmable. See section on Programmable Flag Offset Loading.
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write
operations. If no reads are performed after a reset, FF will go LOW after D writes
to the FIFO. D = 1,024 writes for the IDT72V3640, 2,048 writes for the
IDT72V3650, 4,096 writes for the IDT72V3660, 8,192 writes for the IDT72V3670,
16,384 writes for the IDT72V3680 and 32,768 writes for the IDT72V3690,
respectively.

72V3640L6BB

Mfr. #:
Manufacturer:
IDT
Description:
FIFO 3.3V 32K X 36 SSII
Lifecycle:
New from this manufacturer.
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