34
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II
TM
36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
In IDT Standard mode: D = 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660 and 8,192 for the IDT72V3670, 16,384 for the IDT72V3680 and 32,768
for the IDT72V3690.
In FWFT mode: D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680 and 32,769 for the
IDT72V3690.
3.
t
SKEW2
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t
PAFS
). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than t
SKEW2
, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
WCLK
WEN
PAF
RCLK
(3)
t
PAFS
REN
4667 drw23
D - (m+1) words in FIFO
(2)
D - m words in FIFO
(2)
1
2
12
D-(m+1) words
in FIFO
(2)
t
PAFS
t
ENH
t
ENS
t
SKEW2
t
ENH
t
ENS
t
CLKL
t
CLKL
RCLK
LD
REN
Q
0
- Q
n
tLDH
tLDS
tENS
DATA IN OUTPUT REGISTER PAE OFFSET
PAF OFFSET
tENH
tENH
tLDH
4667 drw22
t
CLK
tA
tA
tCLKH tCLKL
WCLK
LD
WEN
D
0 - Dn
4667 drw21
t
LDS
t
ENS
PAE
OFFSET
PAF
OFFSET
t
DS
t
DH
t
LDH
t
ENH
t
CLK
t
LDH
t
ENH
t
DH
t
CLKH
t
CLKL
Figure 18. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
NOTES:
1. OE = LOW.
2. The timing diagram illustrates reading of offset registers with an output bus width of 36 bits.
Figure 17. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
Figure 16. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
NOTE:
1. This timing diagram illustrates programming with an input bus width of 36 bits.
