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72V3640L6BB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46
7
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II
TM
36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
NOTE:
1. Inputs should not change state after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 42-45 and Figures 31-33.
PIN DESCRIPTION (PBGA PACKAGE ONLY)
Symbol Name I/O Description
ASYR
(1)
Asynchronous I A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW
Read Port will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode.
ASYW
(1)
Asynchronous I A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW
Write Port will select Asynchronous operation.
TCK
(2)
JTAG Clock I Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the
device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and outputs change
on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND.
TDI
(2)
JTAG Test Data I One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data
Input serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register and Bypass Register.
An internal pull-up resistor forces TDI HIGH if left unconnected.
TDO
(2)
JTAG Test Data O One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data
Output serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID Register and Bypass
Register. This output is high impedance except when shifting, while in SHIFT-DR and SHIFT-IR controller states.
TMS
(2)
JTAG Mode Select I TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through
its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
TRST
(2)
JTAG Reset I TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically reset
upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles. If the TAP
controller is not properly reset then the FIFO outputs will always be in high-impedance. If the JTAG function is used
but the user does not want to use TRST, then TRST can be tied with MRS to ensure proper FIFO operation. If the
JTAG function is not used then this signal needs to be tied to GND.
PIN DESCRIPTION-CONTINUED (TQFP & PBGA PACKAGES)
SEN Serial Enable I SEN enables serial loading of programmable flag offsets.
WCLK/ Write Clock/ I If Synchronous operation of the write port has been selected, when enabled by WEN, the rising edge of WCLK
WR Write Strobe writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into the FIFO
on a rising edge in an Asynchronous manner, (WEN should be tied to its active state). Asynchronous operation of
the WCLK/WR input is only available in the PBGA package.
WEN Write Enable I WEN enables WCLK for writing data into the FIFO memory and offset registers.
VCC +3.3V Supply I These are VCC supply inputs and must be connected to the 3.3V supply rail.
Symbol Name I/O Description
NOTE:
1. Inputs should not change state after Master Reset.
8
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II
TM
36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
ABSOLUTE MAXIMUM RATINGS
Symbol Rating Com’l & Ind’l Unit
V
TERM
(2)
Terminal Voltage –0.5 to +4.5 V
with respect to GND
T
STG Storage –55 to +125 °C
Temperature
I
OUT DC Output Current –50 to +50 mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC terminal only.
NOTES:
1. With output deselected, (OE ≥ V
IH).
2. Characterized values, not currently tested.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter
(1)
Conditions Max. Unit
CIN
(2)
Input VIN = 0V 10 pF
Capacitance
C
OUT
(1,2)
Output VOUT = 0V 10 pF
Capacitance
Symbol Parameter Min. Typ. Max. Unit
VCC
(1)
Supply Voltage Com’l/Ind’l 3.15 3.3 3.45 V
GND Supply Voltage Com’l/Ind’l 0 0 0 V
V
IH
(2)
Input High Voltage Com’l/Ind’l 2.0 — 5.5 V
V
IL
(3)
Input Low Voltage Com’l/Ind’l — — 0.8 V
TA Operating Temperature 0 — 70 °C
Commercial
T
A Operating Temperature -40 — 85 °C
Industrial
NOTES:
1. VCC = 3.3V ± 0.15V, JEDEC JESD8-A compliant.
2. Outputs are not 5V tolerant.
3. 1.5V undershoots are allowed for 10ns once per cycle.
IDT72V3640L
IDT72V3650L
IDT72V3660L
IDT72V3670L
IDT72V3680L
IDT72V3690L
Commercial and Industrial
(1)
tCLK = 6, 7-5, 10, 15 ns
Symbol Parameter Min. Max. Unit
ILI
(2)
Input Leakage Current –1 1 μA
ILO
(3)
Output Leakage Current –10 10 μA
VOH Output Logic “1” Voltage, IOH = –2 mA 2.4 — V
VOL Output Logic “0” Voltage, IOL = 8 mA — 0.4 V
ICC1
(4,5,6)
Active Power Supply Current — 40 mA
I
CC2
(4,7)
Standby Current — 15 mA
NOTES:
1. Industrial temperature range product for the 7-5ns and 15ns speed grades are available as a standard device. All other speed grades are available by special order.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs open (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical ICC1 = 4.2 + 1.4*fS + 0.002*CL*fS (in mA) with VCC = 3.3V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2,
CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
RECOMMENDED DC OPERATING
CONDITIONS
9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II
TM
36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
AC ELECTRICAL CHARACTERISTICS
(1)
— SYNCHRONOUS TIMING
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range product for 7-5ns and 15ns speed grades are available as standard device. All other speed grades are available by special order.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
5. TQFP package only: for speed grades 7.5ns, 10ns and 15ns, the minimum for tA, tOE, and tOHZ is 2ns.
Commercial Com’l & Ind’l
(2)
Commercial Com’l & Ind’l
(2)
PBGA & TQFP PBGA & TQFP TQFP Only TQFP Only
IDT72V3640L6 IDT72V3640L7-5 IDT72V3640L10 IDT72V3640L15
IDT72V3650L6 IDT72V3650L7-5 IDT72V3650L10 IDT72V3650L15
IDT72V3660L6 IDT72V3660L7-5 IDT72V3660L10 IDT72V3660L15
IDT72V3670L6 IDT72V3670L7-5 IDT72V3670L10 IDT72V3670L15
IDT72V3680L6 IDT72V3680L7-5 IDT72V3680L10 IDT72V3680L15
IDT72V3690L6 IDT72V3690L7-5 IDT72V3690L10 IDT72V3690L15
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
fS Clock Cycle Frequency — 166 — 133.3 — 100 — 66.7 MH z
tA Data Access Time
(5)
141
(5)
51
(5)
6.5 1
(5)
10 ns
tCLK Clock Cycle Time 6 — 7.5 — 10 — 15 — ns
tCLKH Clock High Time 2.7 — 3.5 — 4.5 — 6 — ns
tCLKL Clock Low Time 2.7 — 3.5 — 4.5 — 6 — ns
tDS Data Setup Time 2 — 2.5 — 3.5 — 4 — ns
tDH Data Hold Time 0.5 — 0.5 — 0.5 — 1 — ns
tENS Enable Setup Time 2 — 2.5 — 3.5 — 4 — ns
tENH Enable Hold Time 0.5 — 0.5 — 0.5 — 1 — ns
tLDS Load Setup Time 3 — 3.5 — 3.5 — 4 — ns
tLDH Load Hold Time 0.5 — 0.5 — 0.5 — 1 — ns
tRS Reset Pulse Width
(3)
10 — 10 — 10 — 15 — ns
tRSS Reset Setup Time 15 — 15 — 15 — 15 — ns
tRSR Reset Recovery Time 10 — 10 — 10 — 15 — ns
tRSF Reset to Flag and Output Time — 15 — 15 — 15 — 15 ns
tRTS Retransmit Setup Time 3 — 3.5 — 3.5 — 4 — ns
tOLZ Output Enable to Output in Low Z
(4)
0—0—0 —0—ns
tOE Output Enable to Output Valid
(5)
141
(5)
61
(5)
61
(5)
8ns
tOHZ Output Enable to Output in High-Z
(4, 5)
141
(5)
61
(5)
61
(5)
8ns
tWFF Write Clock to FF or IR —4—5—6.5—10ns
tREF Read Clock to EF or OR —4—5—6.5—10ns
tPAFA Clock to Asynchronous Programmable Almost-Full Flag — 10 — 12.5 — 16 — 20 ns
tPAFS Write Clock to Synchronous Programmable Almost-Full Flag — 4 — 5 — 6.5 — 10 ns
tPAEA Clock to Asynchronous Programmable Almost-Empty Flag — 10 — 12.5 — 16 — 20 ns
tPAES Read Clock to Synchronous Programmable Almost-Empty Flag — 4 — 5 — 6.5 — 10 ns
tHF Clock to HF — 10 — 12.5 — 16 — 20 ns
tSKEW1 Skew time between RCLK and WCLK for EF/OR and FF/IR 4—5—7 —9—ns
tSKEW2 Skew time between RCLK and WCLK for PAE and PAF 5—7—10 —14—ns
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46

72V3640L6BB

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Buy 72V3640L6BB
Manufacturer:
IDT
Description:
FIFO 3.3V 32K X 36 SSII
Lifecycle:
New from this manufacturer.
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