XA6SLX25T-2CSG324Q

XA Spartan-6 Automotive FPGA Family Overview
DS170 (v1.3) December 13, 2012 www.xilinx.com
Product Specification 7
Low-Power Gigabit Transceiver
Ultra-fast data transmission between ICs, over the backplane, or over longer distances is becoming increasingly popular and
important. It requires specialized dedicated on-chip circuitry and differential I/O capable of coping with the signal integrity
issues at these high data rates.
All XA Spartan-6 LXT devices have 2–4 gigabit transceiver circuits. Each GTP transceiver is a combined transmitter and
receiver capable of operating at data rates up to 3.2 Gb/s. The transmitter and receiver are independent circuits that use
separate PLLs to multiply the reference frequency input by certain programmable numbers between 2 and 25, to become
the bit-serial data clock. Each GTP transceiver has a large number of user-definable features and parameters. All of these
can be defined during device configuration, and many can also be modified during operation.
Transmitter
The transmitter is fundamentally a parallel-to-serial converter with a conversion ratio of 8, 10, 16, or 20. The transmitter
output drives the PC board with a single-channel differential current-mode logic (CML) output signal.
TXOUTCLK is the appropriately divided serial data clock and can be used directly to register the parallel data coming from
the internal logic. The incoming parallel data is fed through a small FIFO and can optionally be modified with the 8B/10B
algorithm to guarantee a sufficient number of transitions. The bit-serial output signal drives two package pins with
complementary CML signals. This output signal pair has programmable signal swing as well as programmable pre-
emphasis to compensate for PC board losses and other interconnect characteristics.
Receiver
The receiver is fundamentally a serial-to-parallel converter, changing the incoming bit serial differential signal into a parallel
stream of words, each 8, 10, 16, or 20 bits wide. The receiver takes the incoming differential data stream, feeds it through a
programmable equalizer (to compensate for the PC board and other interconnect characteristics), and uses the F
REF
input
to initiate clock recognition. There is no need for a separate clock line. The data pattern uses non-return-to-zero (NRZ)
encoding and optionally guarantees sufficient data transitions by using the 8B/10B encoding scheme. Parallel data is then
transferred into the FPGA logic using the RXUSRCLK clock. The serial-to-parallel conversion ratio can be 8, 10, 16, or 20.
Integrated Endpoint Block for PCI Express Designs
The PCI Express standard is a packet-based, point-to-point serial interface standard. The differential signal transmission
uses an embedded clock, which eliminates the clock-to-data skew problems of traditional wide parallel buses.
The PCI Express Base Specification 1.1 defines bit rate of 2.5 Gb/s per lane, per direction (transmit and receive). When
using 8B/10B encoding, this supports a data rate of 2.0 Gb/s per lane.
The XA Spartan-6 LXT devices include one integrated Endpoint block for PCI Express technology that is compliant with the
PCI Express Base Specification Revision 1.1. This block is highly configurable to system design requirements and operates
as a compliant single lane Endpoint. The integrated Endpoint block interfaces to the GTP transceivers for serialization/de-
serialization, and to block RAMs for data buffering. Combined, these elements implement the physical layer, data link layer,
and transaction layer of the protocol.
Xilinx provides a light-weight (<200 LUT), configurable, easy-to-use LogiCORE™ IP that ties the various building blocks (the
integrated Endpoint block for PCI Express technology, the GTP transceivers, block RAM, and clocking resources) into a
compliant Endpoint solution. The system designer has control over many configurable parameters: maximum payload size,
reference clock frequency, and base address register decoding and filtering.
More information and documentation on solutions for PCI Express designs can be found at:
http://www.xilinx.com/technology/protocols/pciexpress.htm
XA Spartan-6 Automotive FPGA Family Overview
DS170 (v1.3) December 13, 2012 www.xilinx.com
Product Specification 8
XA Spartan-6 FPGA Ordering Information
Table 3 shows the speed and temperature grades available in the different XA Spartan-6 devices. Some devices might not
be available in every speed and temperature grade.
The XA Spartan-6 FPGA ordering information shown in Figure 1 applies to all packages. All XA Spartan-6 FPGA products
are offered in Pb-Free packages only. Refer to the Package Marking section of UG385
, Spartan-6 FPGA Packaging and
Pinouts for a more detailed explanation of the device markings.
Revision History
The following table shows the revision history for this document:
Table 3: Speed Grade and Temperature Ranges
Device Family
Speed Grade and Temperature Range
I-Grade Q-Grade
–40°C to +100°C –40°C to +125°C
XA Spartan-6 LX -2, -3 -2, -3
(1)
XA Spartan-6 LXT -2, -3 -2, -3
(1)
Notes:
1. The Q-Grade speed files are named -2Q and -3Q.
X-Ref Target - Figure 1
Figure 1: XA Spartan-6 FPGA Ordering Information
Date Version Description of Revisions
03/02/10 1.0 Initial Xilinx release.
08/23/11 1.1 Changed document classification to Preliminary Product Specification. Updated General Description.
Updated Summary of XA Spartan-6 FPGA Features. Added XA6SLX100
to Tabl e 1 and Tabl e 2 .
Updated Configuration. Removed Dynamic Reconfiguration Port. Updated Clock Management, PLL,
Block RAM, Programmable Data Width, Digital Signal Processing—DSP48A1 Slice, Input/Output,
Input and Output Delay, Low-Power Gigabit Transceiver, and Integrated Endpoint Block for PCI
Express Designs. Updated Figure 1. Updated XA Spartan-6 FPGA Documentation. Updated Notice of
Disclaimer.
12/13/11 1.2 Changed document classification from Preliminary Product Specification to Product Specification.
Updated XA Spartan-6 FPGA Ordering Information.
12/13/12 1.3 Added CSG484 package for XA6SLX45 & XA6SLX75 in Tabl e 1 , Ta bl e 2 , and updated Input/Output.
Example: XA6SLX75T-2FGG484I
Temperature Range:
Q = Q-Grade (T
j
= –40°C to +125°C)
I = I-Grade (T
j
= –40°C to +100°C)
Number of Pins
Package Type
Speed Grade
(-2
(1)
, -3)
Pb-Free
DS170_01_072511
Device Type
Notes:
1) XA6SLX100 is only available in -2 speed grade
.
XA Spartan-6 Automotive FPGA Family Overview
DS170 (v1.3) December 13, 2012 www.xilinx.com
Product Specification 9
Notice of Disclaimer
The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the
maximum extent permitted by applicable law: (1) Materials are made available “AS IS” and with all faults, Xilinx hereby DISCLAIMS
ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES
OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
(whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature
related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect,
special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a
result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the
possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the
Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written
consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at
http://www.xilinx.com/warranty.htm
;
IP cores may be subject to warranty and support terms contained in a license issued to you by
Xilinx.
Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you
assume sole risk and liability for use of Xilinx products in Critical Applications: http://www.xilinx.com/warranty.htm#critapps.
Automotive Applications Disclaimer
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-
SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A
VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN
THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III)
USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY
USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.

XA6SLX25T-2CSG324Q

Mfr. #:
Manufacturer:
Xilinx
Description:
FPGA - Field Programmable Gate Array
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union