XC17V02VQ44C Datasheet XC17V16PC44I, XC17V16PC44C, XC17V16VQ44I | P1-P3

DS073 (v1.12) November 13, 2008 www.xilinx.com

Product Specification 1

other countries. All other trademarks are the property of their respective owners.

Features

• One-time programmable (OTP) read-only memory

designed to store configuration bitstreams of

Xilinx

FPGA devices

• Simple interface to the FPGA

• Cascadable for storing longer or multiple bitstreams

• Programmable reset polarity (active High or active

Low) for compatibility with different FPGA solutions

• Low-power CMOS floating-gate process

• 3.3V supply voltage

• Guaranteed 20 year life data retention

• Available in compact plastic packages: VQ44, PC44,

PC20, VO8, and SO20

(1)

• Programming support by leading programmer

manufacturers

• Design support using the ISE

Foundation™ and

ISE WebPACK™ software

• Dual configuration modes for the XC17V16 and

XC17V08

(1)

devices

♦ Serial slow/fast configuration (up to 20 Mb/s)

♦ Parallel (up to 160 Mb/s at 20 MHz)

Description

Xilinx introduces the high-density XC17V00 family of

configuration PROMs which provide an easy-to-use, cost-

effective method for storing large Xilinx FPGA configuration

bitstreams. Initial devices in the 3.3V family are available in

16 Mb, 8 Mb, 4 Mb, 2 Mb, and 1 Mb densities. See Figure 1

and Figure 2 for simplified block diagrams of the XC17V00

family.

The XC17V00 PROM can configure a Xilinx FPGA using

the FPGA serial configuration mode interface. When the

FPGA is in Master Serial mode, it generates a configuration

clock that drives the PROM. A short access time after the

rising clock edge, data appears on the PROM DATA output

pin that is connected to the FPGA DIN pin. The FPGA

generates the appropriate number of clock pulses to

complete the configuration. Once configured, it disables the

PROM. When the FPGA is in Slave Serial mode, the PROM

and the FPGA must both be clocked by an incoming signal.

The XC17V08

(1)

and XC17V16 PROM can optionally

configure a Xilinx FPGA using the FPGA Parallel

(SelectMAP) configuration mode interface. When the FPGA

is in Master SelectMAP mode, the FPGA generates the

configuration clock that drives the PROM.

When the FPGA is in Slave SelectMAP mode, an external,

free-running oscillator generates the configuration clock

that drives the PROM and the FPGA. After the rising

configuration clock (CCLK) edge, data is available on the

PROMs DATA (D0-D7) pins. The data is clocked into the

FPGA on the following rising edge of the CCLK (Figure 3).

Multiple PROMs can be concatenated by using the CEO

output to drive the CE

input of the following device. The

clock inputs and the DATA outputs of all PROMs in this

chain are interconnected. All devices are compatible and

can be cascaded with other members of the family.

For device programming, either the Xilinx ISE Foundation or

ISE WebPACK software compiles the FPGA design file into

a standard Hex format, which is then transferred to most

commercial PROM programmers.

XC17V00 Series Configuration PROMs

DS073 (v1.12) November 13, 2008

Product Specification

1. Specific part number and package combinations have been discontinued. Refer to XCN07010. Discontinued part number and package combinations

remain in this data sheet for reference.

XC17V00 Series Configuration PROMs

DS073 (v1.12) November 13, 2008 www.xilinx.com

Product Specification 2

X-Ref Target - Figure 1

Figure 1: Simplified Block Diagram for XC17V04, XC17V02

(1)

, and XC17V01

(does not show programming circuit)

X-Ref Target - Figure 2

Figure 2: Simplified Block Diagram for XC17V16 and XC17V08

(1)

(does not show programming circuit)

EPROM

Cell

Matrix

Address Counter

DATA

Output

CLK

GND

DS073_01_072600

RESET/

OE/

RESET

CEO

EPROM

Cell

Matrix

Address Counter

D0 Data

(Serial or Parallel Mode)

Output

CLK

BUSY

GND

DS073_02_031506

RESET/

OE/

RESET

D[1:7]

(SelectMAP Interface)

CEO

XC17V00 Series Configuration PROMs

DS073 (v1.12) November 13, 2008 www.xilinx.com

Product Specification 3

Pin Description

DATA[0:7]

The array data value corresponding to the internal address

counter location is output on enabled DATA[0-7] output

pin(s) when CE

is active, OE is active, and the internal

address counter has not incremented beyond its Terminal

Count (TC) value. Otherwise, all data pins are in a high

impedance state when CE

is inactive, OE is inactive, or the

internal address counter has incremented beyond its

Terminal Count (TC) value.

The XC17V01, XC17V02, and XC17V04 have only the

single DATA output pin for connection to the FPGA serial

configuration data input pin.

The XC17V08 and XC17V16 have the D[0-7] output pins.

During device programming, the XC17V08 and XC17V16

must be programmed for use in either serial output mode or

parallel output mode. For XC17V08 and XC17V16 devices

programmed to serial output mode, only the D0 pin is

enabled for data output to the Virtex

series FPGA serial

configuration data input pin. In serial mode, the D[1-7]

output pins remain in high impedance state and may be

unconnected. For XC17V08 and XC17V16 devices

programmed to parallel output mode, all D[0-7] output pins

are enabled for byte-wide data output to the FPGA

SelectMAP configuration data input pins.

The DATA/D0 pin is a bidirectional I/O during device

programming.

CLK

Each rising edge on the CLK input increments the internal

address counter, when CE

is active, OE is active, the

internal address counter has not incremented past its

Terminal Count (TC) value, and BUSY is Low.

Note:

The BUSY condition applies to only the XC17V08 and

XC17V16.

RESET/OE

The polarity of this input pin is programmable as either

RESET/OE

or OE/RESET. The polarity is set at the time of

device programming. The device default is active-High

RESET, but compatibility with Xilinx FPGAs requires the

polarity to be programmed with an active-Low RESET.

When RESET is active, the address counter is held at “0”,

and puts the DATA output in a high-impedance state.

When High, this pin holds the internal address counter in

reset, puts the DATA output in a high-impedance state, and

forces the device into low-I

standby mode.

CEO

Chip Enable Output is connected to the CE input of the next

PROM in the daisy chain. This output is Low when the CE

and OE

inputs are both active AND the internal address

counter has been incremented beyond its Terminal Count

(TC) value. CEO

returns to High when OE goes inactive or

goes High.

BUSY (XC17V16 and XC17V08 Only)

Asserting the BUSY input High prevents rising edges on

CLK from incrementing the internal address counter and

maintains current data on the data pins.

Note:

If the BUSY pin is floating, then the programmable option

to internally tie BUSY to an internal pull-down resistor must be set

during device programming.

Programming voltage. No overshoot above the specified

maximum voltage is permitted on this pin. For normal read

operation, this pin must be connected to V

. Failure to do

so may lead to unpredictable, temperature-dependent

operation and severe problems in circuit debugging.

Caution! Do not leave V

floating!

and GND

Positive supply and ground pins.

PROM Pinouts for XC17V16 and XC17V08

Pins not listed in Table 1 are “no connect.”

Tabl e 1 : Pinouts for XC17V16 and XC17V08

(1)

Pin Name 44-pin VQFP (VQ44) 44-pin PLCC (PC44)

BUSY 24 30

D0 40 2

D1 29 35

D2 42 4

D3 27 33

D4 9 15

D5 25 31

D6 14 20

D7 19 25

CLK 43 5

RESET/OE

(OE/RESET)

13 19

15 21

GND 6, 18, 28, 37, 41 3, 12, 24, 34, 43

CEO 21 27

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

XC17V02VQ44C

Mfr. #:

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