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XC17V02VQ44C

P1-P3P4-P6P7-P9P10-P12P13-P15
XC17V00 Series Configuration PROMs
DS073 (v1.12) November 13, 2008 www.xilinx.com
Product Specification 10
R
Absolute Maximum Ratings
(1)
Operating Conditions (3V Supply)
DC Characteristics Over Operating Condition
Symbol Description Conditions Units
V
CC
Supply voltage relative to GND –0.5 to +7.0 V
V
PP
Supply voltage relative to GND –0.5 to +12.5 V
V
IN
Input voltage relative to GND –0.5 to V
CC
+0.5 V
V
TS
Voltage applied to High-Z output –0.5 to V
CC
+0.5 V
T
STG
Storage temperature (ambient) –65 to +150 °C
T
J
Junction temperature +125 °C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Symbol Description Min Max Units
V
CC
(1)
Supply voltage relative to GND (T
A
= 0°C to +70°C) Commercial 3.0 3.6 V
Supply voltage relative to GND (T
A
= –40°C to +85°C) Industrial 3.0 3.6 V
T
VCC
(2)
V
CC
rise time from 0V to nominal voltage 1.0 50 ms
Notes:
1. During normal read operation V
PP
must be connected to V
CC
.
2. At power up, the device requires the V
CC
power supply to monotonically rise from 0V to nominal voltage within the specified V
CC
rise time. If
the power supply cannot meet this requirement, then the device may not power-on-reset properly.
Symbol Description Min Max Units
V
IH
High-level input voltage 2 V
CC
V
V
IL
Low-level input voltage 0 0.8 V
V
OH
High-level output voltage (I
OH
= –3 mA) 2.4 – V
V
OL
Low-level output voltage (I
OL
= +3 mA) – 0.4 V
I
CCA
Supply current, active mode (at maximum frequency)
(XC17V16 and XC17V08
(1)
only)
– 100
mA
I
CCA
Supply current, active mode (at maximum frequency)
(XC17V04, XC17V02
(1)
, and XC17V01
(1)
only)
–15mA
I
CCS
Supply current, standby mode – 1 mA
I
L
Input or output leakage current –10 10 μA
C
IN
Input capacitance (V
IN
= GND, f = 1.0 MHz) – 15 pF
C
OUT
Output capacitance (V
IN
= GND, f = 1.0 MHz) – 15 pF
Notes:
1. Specific part number and package combinations have been discontinued. Refer to XCN07010.
XC17V00 Series Configuration PROMs
DS073 (v1.12) November 13, 2008 www.xilinx.com
Product Specification 11
R
AC Characteristics over Operating Condition for XC17V04, XC17V02, and
XC17V01
X-Ref Target - Figure 4
Symbol Description Min Max Units
T
OE
OE to data delay – 30 ns
T
CE
CE to data delay – 45 ns
T
CAC
CLK to data delay – 45 ns
T
DF
CE or OE to data float delay
(2,3)
–50ns
T
OH
Data hold from CE, OE, or CLK
(3)
0–ns
T
CYC
Clock periods 67 – ns
T
LC
CLK Low time
(3)
25 – ns
T
HC
CLK High time
(3)
25 – ns
T
SCE
CE setup time to CLK (to guarantee proper counting) 25 – ns
T
HCE
CE hold time to CLK (to guarantee proper counting) 0 – ns
T
HOE
OE hold time (guarantees counters are reset) 25 – ns
T
CEH
CE High time (guarantees counters are reset) 20 – ns
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with V
IL
= 0.0V and V
IH
= 3.0V.
5. If T
CEH
High, 2 μs, T
CE
= 2 μs.
6. If T
HOE
High, 2 μs, T
OE
= 2 μs.
RESET/OE
CE
CLK
DATA
T
CE
T
OE
T
LC
T
SCE
T
SCE
T
HCE
T
HOE
T
CAC
T
OH
T
DF
T
OH
T
HC
DS073_04_14102005
T
CYC
TCEH
Notes:
1 The XC17V00 RESET/OE input polarity is programmable. The RESET/OE input is shown in the timing diagram with active-high
RESET polarity. Timing specifications are identical for both polarity settings.
2 The diagram shows timing relationships. The diagram is not reflective of actual FPGA signal sequences. See the appropriate
FPGA data sheet or user guide for actual configuration signal sequences.
XC17V00 Series Configuration PROMs
DS073 (v1.12) November 13, 2008 www.xilinx.com
Product Specification 12
R
AC Characteristics over Operating Condition for XC17V16 and XC17V08
X-Ref Target - Figure 5
Symbol Description Min Max Units
T
OE
OE to data delay – 15 ns
T
CE
CE to data delay – 20 ns
T
CAC
CLK to data delay
(2)
–20ns
T
DF
CE or OE to data float delay
(3,4)
–35ns
T
OH
Data hold from CE, OE, or CLK
(4)
0–ns
T
CYC
Clock periods 50 – ns
T
LC
CLK Low time
(4)
25 – ns
T
HC
CLK High time
(4)
25 – ns
T
SCE
CE setup time to CLK (to guarantee proper counting) 25 – ns
T
HCE
CE hold time to CLK (to guarantee proper counting) 0 – ns
T
HOE
OE hold time (guarantees counters are reset) 25 – ns
T
SBUSY
BUSY setup time 5 – ns
T
HBUSY
BUSY hold time 5 – ns
T
CEH
CE High time (guarantees counters are reset) 20 – ns
Notes:
1. AC test load = 50 pF.
2. When BUSY = 0.
3. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
4. Guaranteed by design, not tested.
5. All AC parameters are measured with V
IL
= 0.0V and V
IH
= 3.0V.
6. If T
CEH
High, 2 μs, T
CE
= 2 μs.
7. If T
HOE
High, 2 μs, T
OE
= 2 μs.
RESET/OE
(1)
CE
CLK
BUSY
(2)
DATA
T
CE
T
OE
T
LC
T
SCE
T
SCE
T
HCE
T
HOE
T
CAC
T
SBUSY
T
HBUSY
T
OH
T
DF
T
OH
T
HC
DS073_05_031606
T
CYC
TCEH
Note:
1 The XC17V00 RESET/OE input polarity is programmable. The RESET/OE input is shown in the timing diagram with active-high RESET polarity.
Timing specifications are identical for both polarity settings.
2. If BUSY is inactive (Low) during a rising CLK edge, then new DATA appears at time T
CAC
after the rising CLK edge. If BUSY is active (High)
during a rising CLK edge, then there is no corresponding change to DATA.
P1-P3P4-P6P7-P9P10-P12P13-P15

XC17V02VQ44C

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