XC17V00 Series Configuration PROMs
DS073 (v1.12) November 13, 2008 www.xilinx.com
Product Specification 13
R
AC Characteristics over Operating Condition When Cascading
Ordering Information
X-Ref Target - Figure 6
Symbol Description Min Max Units
T
CDF
CLK to data float delay
(2,3)
–50ns
T
OCK
CLK to CEO delay
(3)
–30ns
T
OCE
CE to CEO delay
(3)
–35ns
T
OOE
RESET/OE to CEO delay
(3)
–30ns
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with V
IL
= 0.0V and V
IH
= 3.0V.
CLK
DATA
CE
CEO
First Bit
Last Bit
T
CDF
DS026_07_102005
RESET/OE
T
OCK
T
OOE
T
OCE
Notes:
1 The XC17V00 RESET/OE input polarity is programmable. The RESET/OE input is shown in the timing diagram with active-high
RESET polarity. Timing specifications are identical for both polarity settings.
2 The diagram shows timing of the First Bit and Last Bit for one PROM with respect to signals involved in a cascaded situation.
The diagram does not show timing of data as one PROM transfers control to the next PROM. The shown timing information must
be applied appropriately to each PROM in a cascaded situation to understand the timing of data during the transfer of control
from one PROM to the next.
XC17V16 PC44 C
Operating Range/Processing
C = Commercial (T
A
=
0° to +70°C)
I = Industrial (T
A
= –40° to +85°C)
Package Type
VQ44 = 44-pin Plastic Quad Flat Package
PC44 = 44-pin Plastic Chip Carrier
VO8 = 8-pin Plastic Small Outline Thin Package
PC20 = 20-pin Plastic Leaded Chip Carrier
Device Number
XC17V16
XC17V04
XC17V01
XC17V00 Series Configuration PROMs
DS073 (v1.12) November 13, 2008 www.xilinx.com
Product Specification 14
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Valid Ordering Combinations
Marking Information
Due to the small size of the commercial serial PROM packages, the complete ordering part number cannot be marked on
the package. The XC prefix is deleted and the package code is simplified. Device marking is as follows:
XC17V16VQ44C XC17V04PC20C XC17V01VO8C
XC17V16PC44C XC17V04PC44C
XC17V16VQ44I XC17V04VQ44C
XC17V16PC44I XC17V04PC20I
XC17V04PC44I
XC17V04VQ44I
XC17V16 PC44 C
Operating Range/Processing
C=Commercial (T
A
=
0° to +70°C)
I = Industrial (T
A
= –40° to +85°C)
Package Type
VQ44 = 44-pin Plastic Quad Flat Package
PC44 = 44-pin Plastic Chip Carrier
VO8 = 8-pin Plastic Small Outline Thin Package
PC20 = 20-pin Plastic Leaded Chip Carrier
SO20 = 20-pin Plastic Small Outline Package
(1)
Device Number
XC17V16
XC17V08
(1)
XC17V04
XC17V02
(1)
XC17V01
Notes:
1. Specific part number and package combinations have been discontinued. Refer to XCN07010.
XC17V00 Series Configuration PROMs
DS073 (v1.12) November 13, 2008 www.xilinx.com
Product Specification 15
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Revision History
The following table shows the revision history for this document.
.
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm
. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Date Version Revision
07/26/00 1.0 Initial Xilinx release.
10/09/00 1.1 Updated 20-pin PLCC Pinouts.
11/16/00 1.2 Updated pinouts for XC17V16 and XC17V08, I
CCA
DC Characteristic from standby to active mode; C
IN
and C
OUT
from 10 pF to 15 pF, added I
CCS
for XC17V16 and XC17V08 at 500 μA.
02/20/01 1.3 Added note to pinouts for “no connect,” updated Figure 3.
04/04/01 1.4 Added XC2V products to Compatible PROM table, updated Figure 3, updated text for Virtex-II FPGAs.
10/09/01 1.5 Corrected bitstream length for SCV405E, added power-on supply requirements and note for power-on
reset, updated configuration bits for Virtex-II devices, removed CF from Figure 3, and updated FPGA list.
02/27/02 1.6 Added Virtex-II Pro™ FPGAs to the , page 6.
06/14/02 1.7 Made additions and changes to Xilinx FPGAs and Compatible PROMs, page 6.
07/29/02 1.8 Added Virtex-II Pro FPGAs to , page 6.
11/05/02 1.9 Added pinout diagrams, changed , page 6, and added footnotes to AC Characteristics over Operating
Condition for XC17V04, XC17V02, and XC17V01, page 11 and AC Characteristics over Operating
Condition for XC17V16 and XC17V08, page 12.
04/10/03 1.10 Added Spartan-3 FPGAs to Truth Table for XC17V00 Control Inputs, page 8.
06/07/07 1.11 Figure 2, page 2 updated to show correct three-state control on output data buses.
Corrected XC3S50 bitstream size in Xilinx FPGAs and Compatible PROMs, page 6.
Added section Selecting Reset Polarity and Configuration Modes, page 7.
Removed maximum soldering temperature (T
SOL
) from "Absolute Maximum Ratings
(1)
," page 10.
Refer to Xilinx Device Package User Guide for package soldering guidelines.
Added notes to timing diagram under AC Characteristics over Operating Condition for XC17V04,
XC17V02, and XC17V01, page 11 for clarification.
Added notes and updated timing diagram AC Characteristics over Operating Condition for XC17V16
and XC17V08, page 12 for clarification.
Reversed polarity of RESET/OE signal in timing diagram under , page 13 for consistency and added
notes for clarification.
11/13/08 1.12 Added support for discontinued device and package combinations per XCN07010
.
Added T
J
to "Absolute Maximum Ratings
(1)
," page 10.
Updated Figure 3.

XC17V02VQ44C

Mfr. #:
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Xilinx
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