Document Number: 002-10221 Rev. *B Page 6 of 17
Slave Device Address
The first byte that the CY15B064J expects after a START
condition is the slave address. As shown in Figure 6, the slave
address contains the device type or slave ID, the device select
address bits, and a bit that specifies if the transaction is a read
or a write.
Bits 7–4 are the device type (slave ID) and should be set to
1010b for the CY15B064J. These bits allow other function types
to reside on the I
2
C bus within an identical address range. Bits
3–1 are the device select address bits. They must match the
corresponding value on the external address pins to select the
device. Up to eight CY15B064J devices can reside on the same
I
2
C bus by assigning a different address to each. Bit 0 is the
read/write bit (R/W
). R/W = ‘1’ indicates a read operation and
R/W
= ‘0’ indicates a write operation.
Addressing Overview
After the CY15B064J (as receiver) acknowledges the slave
address, the master can place the memory address on the bus
for a write operation. The address requires two bytes. The
complete 13-bit address is latched internally. Each access
causes the latched address value to be incremented automati-
cally. The current address is the value that is held in the latch;
either a newly written value or the address following the last
access. The current address will be held for as long as power
remains or until a new value is written. Reads always use the
current address. A random read address can be loaded by
beginning a write operation as explained below.
After transmission of each data byte, just prior to the
acknowledge, the CY15B064J increments the internal address
latch. This allows the next sequential byte to be accessed with
no additional addressing. After the last address (1FFFh) is
reached, the address latch will roll over to 0000h. There is no
limit to the number of bytes that can be accessed with a single
read or write operation.
Data Transfer
After the address bytes have been transmitted, data transfer
between the bus master and the CY15B064J can begin. For a
read operation the CY15B064J will place 8 data bits on the bus
then wait for an acknowledge from the master. If the
acknowledge occurs, the CY15B064J will transfer the next
sequential byte. If the acknowledge is not sent, the CY15B064J
will end the read operation. For a write operation, the
CY15B064J will accept 8 data bits from the master then send an
acknowledge. All data transfer occurs MSB (most significant bit)
first.
Memory Operation
The CY15B064J is designed to operate in a manner very similar
to other I
2
C interface memory products. The major differences
result from the higher performance write capability of F-RAM
technology. These improvements result in some differences
between the CY15B064J and a similar configuration EEPROM
during writes. The complete operation for both writes and reads
is explained below.
Write Operation
All writes begin with a slave address, then a memory address.
The bus master indicates a write operation by setting the LSB of
the slave address (R/W
bit) to a '0'. After addressing, the bus
master sends each byte of data to the memory and the memory
generates an acknowledge condition. Any number of sequential
bytes may be written. If the end of the address range is reached
internally, the address counter will wrap from 1FFFh to 0000h.
Unlike other nonvolatile memory technologies, there is no
effective write delay with F-RAM. Since the read and write
access times of the underlying memory are the same, the user
experiences no delay through the bus. The entire memory cycle
occurs in less time than a single bus clock. Therefore, any
operation including read or write can occur immediately following
a write. Acknowledge polling, a technique used with EEPROMs
to determine if a write is complete is unnecessary and will always
return a ready condition.
Internally, an actual memory write occurs after the 8th data bit is
transferred. It will be complete before the acknowledge is sent.
Therefore, if the user desires to abort a write without altering the
memory contents, this should be done using START or STOP
condition prior to the 8th data bit. The CY15B064J uses no page
buffering.
The memory array can be write-protected using the WP pin.
Setting the WP pin to a HIGH condition (V
DD
) will write-protect
all addresses. The CY15B064J will not acknowledge data bytes
that are written to protected addresses. In addition, the address
counter will not increment if writes are attempted to these
addresses. Setting WP to a LOW state (V
SS
) will disable the write
protect. WP is pulled down internally.
Figure 7 and Figure 8 on page 7 below illustrate a single-byte
and multiple-byte write cycles.
Figure 6. Memory Slave Device Address
Slave ID
10
1
0
A2 A0A1
Device Select
Figure 7. Single-Byte Write
S ASlave Address 0 Address MSB A Data Byte A P
By Master
By F-RAM
Start Address & Data
Stop
Acknowledge
Address LSB A
