ADUM5400ARWZ Datasheet ADUM5400ARWZ, ADUM5400CRWZ, ADUM5400ARWZ-RL | P13-P15

ADuM5400 Data Sheet

Rev. B | Page 12 of 16

APPLICATIONS INFORMATION

The dc-to-dc converter section of the ADuM5400 works on

principles that are common to most modern power supplies. It

has a secondary side controller architecture with isolated pulse-

width modulation (PWM) feedback. V

DD1

power is supplied to

an oscillating circuit that switches current into a chip scale air

core transformer. Power transferred to the secondary side is

rectified and regulated to 5 V. The secondary (V

ISO

) side

controller regulates the output by creating a PWM control

signal that is sent to the primary (V

DD1

) side by a dedicated

iCoupler data channel. The PWM modulates the oscillator

circuit to control the power being sent to the secondary side.

Feedback allows for significantly higher power and efficiency.

The ADuM5400 implements undervoltage lockout (UVLO)

with hysteresis on the V

DD1

, V

DDL

, and V

ISO

power supplies. This

feature ensures that the converter does not enter oscillation due

to noisy input power or slow power-on ramp rates.

PCB LAYOUT

The ADuM5400 digital isolator with integrated 0.5 W isoPower

dc-to-dc converter requires no external interface circuitry for the

logic interfaces. Power supply bypassing is required at the input

and output supply pins (see Figure 13). Note that a low ESR bypass

capacitor is required between Pin 1 and Pin 2, within 2 mm of

the chip leads.

The power supply section of the ADuM5400 uses a 180 MHz

oscillator frequency to efficiently pass power through its chip

scale transformers. In addition, normal operation of the data

section of the iCoupler introduces switching transients on the

power supply pins. Bypass capacitors are required and must

provide transient suppression at several operating frequencies.

Noise suppression requires a low inductance, high frequency

capacitor that is effective at 180 MHz and 360 MHz. Ripple

suppression and proper regulation require a large value capacitor

to provide bulk current at 625 kHz. These are most conveniently

connected between Pin 1 and Pin 2 for V

DD1

and between Pin 15

and Pin 16 for V

ISO

. To suppress noise and reduce ripple, a

parallel combination of at least two capacitors is required. The

recommended capacitor values are 0.1 μF and 10 μF for V

DD1

The smaller capacitor must have low ESR; for example, use of a

ceramic capacitor is advised.

Note that the total lead length between the ends of the low ESR

capacitor and the input power supply pin must not exceed 2 mm.

Installing the bypass capacitor with traces more than 2 mm in

length may result in data corruption. Consider a bypass capacitor

between Pin 1 and Pin 8 and between Pin 9 and Pin 16 unless

both common ground pins are connected together close to the

package.

DD1

GND

ISO

GND

ISO

DDL

ISO

GND

BYPASS < 2mm

GND

ISO

07509-017

ADuM5400

Figure 13. Recommended PCB Layout

In applications involving high common-mode transients, ensure

that board capacitive coupling across the isolation barrier is

minimized. Furthermore, design the board layout so that any

coupling that does occur affects all pins on a given component

side equally. Failure to ensure this can cause differential voltages

between pins, exceeding the absolute maximum ratings for the

device (specified in Table 10) and thereby leading to latch-up

and/or permanent damage.

The ADuM5400 is a power device that dissipates about 1 W

of power when fully loaded and running at maximum speed.

Because it is not possible to apply a heat sink to an isolation

device, the device depends primarily on heat dissipation into

the PCB through the GND pins. If the device is used at high

ambient temperatures, provide a thermal path from the GND

pins to the PCB ground plane. The board layout in Figure 13

shows enlarged pads for Pin 8 (GND

) and Pin 9 (GND

ISO

Large diameter vias should be implemented from the pad to the

ground, and power planes should be used to reduce inductance.

Multiple vias in the thermal pads can significantly reduce temper-

atures inside the chip. The dimensions of the expanded pads are

at the discretion of the designer and depend on the available

board space.

EMI CONSIDERATIONS

The dc-to-dc converter section of the ADuM5400 component

must operate at a very high frequency to allow efficient power

transfer through the small transformers. This creates high

frequency currents that can propagate in circuit board ground

and power planes, causing edge emissions and dipole radiation

between the primary and secondary ground planes. Grounded

enclosures are recommended for applications that use these

devices. If grounded enclosures are not possible, follow good

RF design practices in the layout of the PCB. See the AN-0971

Application Note for board layout recommendations.

Data Sheet ADuM5400

Rev. B | Page 13 of 16

PROPAGATION DELAY PARAMETERS

Propagation delay is a parameter that describes the time it takes a

logic signal to propagate through a component (see Figure 14).

The propagation delay to a logic low output may differ from the

propagation delay to a logic high output.

INPUT (V

)

OUTPUT (V

)

PLH

PHL

50%

07509-018

Figure 14. Propagation Delay Parameters

Pulse width distortion is the maximum difference between

these two propagation delay values and is an indication of how

accurately the timing of the input signal is preserved.

Channel-to-channel matching refers to the maximum amount

that the propagation delay differs between channels within a

single ADuM5400 component.

Propagation delay skew refers to the maximum amount that

the propagation delay differs between multiple ADuM540x

components operating under the same conditions.

DC CORRECTNESS AND MAGNETIC FIELD

IMMUNITY

Positive and negative logic transitions at the isolator input cause

narrow (~1 ns) pulses to be sent to the decoder via the trans-

former. The decoder is bistable and is, therefore, either set or

reset by the pulses, indicating input logic transitions. In the

absence of logic transitions at the input for more than 1 µs,

periodic sets of refresh pulses indicative of the correct input

state are sent to ensure dc correctness at the output. If the decoder

receives no internal pulses for more than approximately 5 µs,

the input side is assumed to be unpowered or nonfunctional, in

which case the isolator output is forced to a default state by the

watchdog timer circuit. This situation should occur in the

ADuM5400 only during power-up and power-down operations.

The limitation on the ADuM5400 magnetic field immunity is

set by the condition in which induced voltage in the receiving

coil of the transformer is sufficiently large to falsely set or reset

the decoder. The following analysis defines the conditions

under which this can occur.

The 3.3 V operating condition of the ADuM5400 is examined

because it represents the most susceptible mode of operation.

The pulses at the transformer output have an amplitude of >1.0 V.

The decoder has a sensing threshold of about 0.5 V, thus estab-

lishing a 0.5 V margin in which induced voltages can be tolerated.

The voltage induced across the receiving coil is given by

V = (−dβ/dt)

∑πr

; n = 1, 2, … , N

where:

β is the magnetic flux density (gauss).

N is the number of turns in the receiving coil.

is the radius of the n

turn in the receiving coil (cm).

Given the geometry of the receiving coil in the ADuM5400 and

an imposed requirement that the induced voltage be, at most,

50% of the 0.5 V margin at the decoder, a maximum allowable

magnetic field is calculated as shown in Figure 15.

MAGNETIC FIELD FREQUENCY (Hz)

100

MAXIMUM ALLOWABLE MAGNETIC FLUX

DENSITY (kgauss)

0.001

0.01

1k 10k 10M

0.1

100M

100k

07509-019

Figure 15. Maximum Allowable External Magnetic Flux Density

For example, at a magnetic field frequency of 1 MHz, the

maximum allowable magnetic field of 0.2 kgauss induces a

voltage of 0.25 V at the receiving coil. This is about 50% of the

sensing threshold and does not cause a faulty output transition.

Similarly, if such an event occurs during a transmitted pulse

(and is of the worst-case polarity), the received pulse is reduced

from >1.0 V to 0.75 V, which is still well above the 0.5 V sensing

threshold of the decoder.

The preceding magnetic flux density values correspond to

specific current magnitudes at given distances from the

ADuM5400 transformers. Figure 16 expresses these allowable

current magnitudes as a function of frequency for selected

distances. As shown in Figure 16, the ADuM5400 is extremely

immune and can be affected only by extremely large currents

operated at high frequency very close to the component. For

example, at a magnetic field frequency of 1 MHz, a 0.5 kA current

placed 5 mm away from the ADuM5400 is required to affect the

operation of the component.

MAGNETIC FIELD FREQUENCY (Hz)

MAXIMUM ALLOWABLE CURRENT (kA)

1000

100

0.1

0.01

1k 10k 100M100k 1M 10M

DISTANCE = 5mm

DISTANCE = 1m

DISTANCE = 100mm

07509-020

Figure 16. Maximum Allowable Current

for Various Current-to-ADuM5400 Spacings

ADuM5400 Data Sheet

Rev. B | Page 14 of 16

Note that in the presence of strong magnetic fields and high

frequencies, any loops formed by PCB traces may induce error

voltages sufficiently large to trigger the thresholds of succeeding

circuitry. Exercise care in the layout of such traces to avoid this

possibility.

POWER CONSUMPTION

The V

DD1

power supply input provides power to the iCoupler

data channels, as well as to the power converter. For this reason,

the quiescent currents drawn by the data converter and the

primary and secondary I/O channels cannot be determined

separately. All of these quiescent power demands have been

combined into the I

DD1(Q)

current, as shown in Figure 17. The

total I

DD1

supply current is equal to the sum of the quiescent

operating current; the dynamic current due to high data rate,

and any external I

ISO

load.

CONVERTER

PRIMARY

CONVERTER

SECONDARY

PRIMARY

DATA

I/O

4-CHANNEL

DDP(D)

SECONDARY

DATA

I/O

4-CHANNEL

ISO(D)

ISO

DD1

7509-021

Figure 17. Power Consumption Within the ADuM5400

Dynamic I/O current is consumed only when operating a channel

at speeds higher than the refresh rate of f

. The dynamic current

of each channel is determined by its data rate. Figure 12 shows

the current for a channel in the forward direction, meaning that

the input is on the V

DD1

side of the part.

The following relationship allows the total I

DD1

current to be

calculated:

DD1

= (I

ISO

× V

ISO

)/(E × V

DD1

) + Σ I

CHn

; n = 1 to 4 (1)

where:

DD1

is the total supply input current.

CHn

is the current drawn by a single channel determined from

Figure 12.

ISO

is the current drawn by the secondary side external load.

E is the power supply efficiency at 100 mA load from Figure 4

at the V

ISO

and V

DD1

condition of interest.

The maximum external load can be calculated by subtracting

the dynamic output load from the maximum allowable load.

ISO(LOAD)

= I

ISO(MAX)

− Σ I

ISO(D)n

; n = 1 to 4 (2)

where:

ISO(LOAD)

is the current available to supply an external secondary

side load.

ISO(MAX)

is the maximum external secondary side load current

available at V

ISO

ISO(D)n

is the dynamic load current drawn from V

ISO

by an

output channel, as shown in Figure 11.

The preceding analysis assumes a 15 pF capacitive load on

each data output. If the capacitive load is larger than 15 pF,

the additional current must be included in the analysis of I

DD1

and I

ISO(LOAD)

POWER CONSIDERATIONS

The ADuM5400 power input, the data input channels on the

primary side, and the data output channels on the secondary side

are all protected from premature operation by UVLO circuitry.

Below the minimum operating voltage, the power converter holds

its oscillator inactive, and all input channel drivers and refresh

circuits are idle. Outputs are held in a low state to prevent trans-

mission of undefined states during power-up and power-down

operations.

During application of power to V

DD1

, the primary side circuitry

is held idle until the UVLO preset voltage is reached.

The primary side input channels sample the input and send a

pulse to the inactive secondary output. As the secondary side

converter begins to accept power from the primary, the V

ISO

voltage starts to rise. When the secondary side UVLO is reached,

the secondary side outputs are initialized to their default low

state until data, either from a logic transition or a dc refresh

cycle, is received from the corresponding primary side input. It

can take up to 1 μs after the secondary side is initialized for the

state of the output to correlate to the primary side input.

The dc-to-dc converter section goes through its own power-up

sequence. When UVLO is reached, the primary side oscillator

also begins to operate, transferring power to the secondary power

circuits. The secondary V

ISO

voltage is below its UVLO limit at

this point; the regulation control signal from the secondary is

not being generated. The primary side power oscillator is allowed

to free run in this circumstance, supplying the maximum amount

of power to the secondary, until the secondary voltage rises to its

regulation setpoint. This creates a large inrush current transient

at V

DD1

. When the regulation point is reached, the regulation

control circuit produces the regulation control signal that mod-

ulates the oscillator on the primary side. The V

DD1

current is

reduced and is then proportional to the load current. The

inrush current is less than the short-circuit current shown in

Figure 7. The duration of the inrush depends on the V

ISO

load

conditions and the current available at the V

DD1

pin.

Because the rate of charge of the secondary side is dependent on

load conditions, the input voltage, and the output voltage level

selected, ensure that the design allows the converter to stabilize

before valid data is required.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

ADUM5400ARWZ

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