MAX5054–MAX5057
4A, 20ns, Dual MOSFET Drivers
14 ______________________________________________________________________________________
Chip Information
PROCESS: CMOS
OUTA
V
DD
OUTB
1
2
8
7
INA+
INB+INB-
GND
INA-
TDFN-EP
TOP VIEW
3
4
6
5
MAX5054
V
DD
OUTBINB-
1
2
8
7
N.C.
OUTAINA-
GND
N.C.
SO/SO-EP
3
4
6
5
MAX5055
V
DD
OUTBINB+
1
2
8
7
N.C.
OUTAINA+
GND
N.C.
SO/SO-EP
3
4
6
5
MAX5056
V
DD
OUTBINB+
1
2
8
7
N.C.
OUTAINA-
GND
N.C.
SO/SO-EP
3
4
6
5
MAX5057
Pin Configurations
Selector Guide
PART
PIN-
PACKAGE
LOGIC INPUT
MAX5054AATA 8 TDFN-EP*
V
DD
/ 2 CMOS Dual Inverting
and Dual Noninverting Inputs
MAX5054BATA 8 TDFN-EP*
TTL Dual Inverting and Dual
Noninverting Inputs
MAX5055AASA 8 SO-EP* TTL Dual Inverting Inputs
MAX5055BASA 8 SO TTL Dual Inverting Inputs
MAX5056AASA 8 SO-EP* TTL Dual Noninverting Inputs
MAX5056BASA 8 SO TTL Dual Noninverting Inputs
MAX5057AASA 8 SO-EP*
TTL Inverting and
Noninverting Inputs
MAX5057BASA 8 SO
TTL Inverting and
Noninverting Inputs
*
EP = Exposed pad.
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages
. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package draw-
ings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE NO.
LAND
PATTERN NO.
8 TDFN-EP T833+2
21-0137
90-0059
8 SO-EP S8E+14
21-0111
90-0151
8 SO S8+4
21-0041 90-0096