LTC4371
10
4371f
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applicaTions inForMaTion
Figure 5. MOSFET Follower for High Voltage >250V
Applications with 5mA Gate Pull-Up Current Disabled
charge is approximately equal to the total gate charge,
Q
g
, as specified on the MOSFETs data sheet.
If there is a fault wherein the MOSFET gate is shorted to V
SS
and ∆V
SD
is large, the 5mA pull-up becomes a continuous
load on V
DD
. The extra V
DD
current overwhelms R
Z
and
discharges the 2.2µF bypass capacitor. When V
Z
falls to
the V
Z(PU_EN)
threshold of 10.7V, the 5mA pull-up current
on both channels is disabled. The 5mA pull-up is enabled
when V
Z
recovers to 11.2V. This feature prevents a shorted
gate pin from collapsing V
DD
and, aside from disabling the
5mA pull-up, interfering with the operation of the second
channel when using the configuration shown in Figure2.
In applications such as Figure3 and 4, if the V
DD
supply is
designed to deliver >5mA, no V
DD
bypassing is required.
Note that a shorted gate will demand a continuous current
of 5mA whenever ∆V
SD
is large.
The 5mA pull-up is enabled when V
Z
is biased to >11.8V
in its normal shunt regulator mode, or when V
Z
is <1.15V.
Connecting V
Z
to V
SS
permanently enables the 5mA gate
pull-up. If V
Z
is not used as a shunt regulator, the 5mA
pull-up can be disabled by biasing V
Z
to voltage between
1.35V and 10.4V (with respect to V
SS
) as shown in Figure5.
the range of 11.6V to 14.1V, compatible with standard
10V-specified MOSFETs. In low voltage applications,
such as where the V
DD
pin is directly powered from less
than 10V, the gate drive is compatible with logic-level
and sub logic-level MOSFETs.
The drain-source breakdown rating, BV
DSS
, must be greater
than or equal to the highest input supply voltage. If an
input is shorted, the full supply voltage of the opposing
channel will appear across the MOSFET of the shorted
channel. Avalanche may occur during input short circuits
and lightning induced surges if the peak transient voltage
exceeds BV
DSS
with respect to V
OUT
.
The LTC4371 attempts to servo the forward drop across
the MOSFET (∆V
SD
) to 15mV by controlling the gate, and
flags a fault if the drop exceeds 200mV when the MOSFET is
driven fully on. Thus an upper bound for R
DS(ON)
is set by:
R
DS(ON)
<
∆V
SD(FLT)
I
LOAD(MAX)
(6)
Where ∆V
SD(FLT)
is 150mV minimum.
Further, R
DS(ON)
must be small enough to conduct the
maximum load current without excessive MOSFET dis-
sipation, which is calculated from:
P
D(MOSFET)
= I
LOAD(MAX)
2
R
DS(ON)
(7)
The definition of “excessive” is provided by the circuit
designer based on package and circuit board thermal
constraints.
Loop Stability
The gate amplifiers are compensated by the input capaci
-
tance of the external MOSFETs. No further compensation
components
are necessar
y except in the case of very small
MOSFETs. If C
ISS
is less than 500pF, add a 1nF capacitor
across the MOSFET gate and source terminals.
High Voltage Transient Protection
Although the LTC4371 drain pins, DA and DB are designed
to handle voltages ranging from –40V to 100V with respect
to V
SS
, they may be subjected to much higher voltages,
even in –48V systems. DA and DB are directly exposed to
MOSFET Selection
The LTC4371 drives N-channel MOSFETs to conduct the
load current. The important features of the MOSFETs are
threshold voltage, V
GS(TH)
; maximum drain-source voltage,
BV
DSS
; and on-resistance, R
DS(ON)
.
Full gate drive for the MOSFETs (V
GATE
) is
V
DD
+100mV/200mV. When used in shunt regulated
circuits such as shown in Figure2, full gate drive lies in
LTC4371
V
Z
V
DD
V
SS
D2
7.5V
R
Z
510k
C1
10nF
RTN
V
OUT
M1
BSP125
D1
7.5V
C2
10nF
4371 F05
R
G
10Ω
LTC4371
11
4371f
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Figure 6. Input Short Circuit Parasitics and Protection Against High Voltage Transients
4371 F06
LTC4371
DA DB GA GB SA
V
Z
V
DD
SB V
SS
FAULTB
2.2μF
20k
20k
OPT.
V
A
–36V TO
–72V
V
B
–36V TO
–72V
V
OUT
GREEN LED =
MOSFETS GOOD
R
Z
30k
33k
RTN
+
+
INPUT PARASITIC
INDUCTANCE
+
OUTPUT PARASITIC
INDUCTANCE
INPUT PARASITIC
INDUCTANCE
INPUT SHORT
C
LOAD
REVERSE
RECOVERY
CURRENT
OPT.
all voltages appearing at the input. Spikes and transients
may arise from various conditions including lightning
induced surges, electrostatic discharge, switching of
adjacent loads, and input short circuits.
The dynamic behavior of an active ideal diode entering
reverse bias is most accurately characterized by a delay,
followed by a period of reverse recovery. During the delay
phase some reverse current is built up, limited by parasitic
resistance and inductance. During the reverse recovery
phase, energy stored in the parasitic inductance is trans
-
ferred to other elements in the circuit.
Current slew rates during reverse recovery may reach
100A
/μs or higher. High slew rates coupled with parasitic
inductance in series with the input and output can cause
destructive transients to appear at the drain, source and
V
SS
pins of the LTC4371 during reverse recovery.
A zero impedance short circuit directly across the input
and return is especially troublesome because it permits
the highest possible reverse current to build up during
the delay phase. When the MOSFET finally interrupts the
reverse current, the MOSFET drain and the LTC4371 drain
pins experience a positive-going voltage spike, while the
MOSFET source and the LTC4371 source and V
SS
pins
spike in the negative direction. To protect the circuit bias-
ing V
DD
, clamp or bypass V
OUT
as close as possible to the
junction of the MOSFET sources and V
SS
and the point
where the V
DD
bias circuit connects to return.
The positive spike at the input is clamped to BV
DSS
rela-
tive to V
OUT
by MOSFET avalanche. BV
DSS
is inadequate
protection for the DA and DB pins, as shall be discussed
later. Although the energy stored in parasitic inductance
during input short circuit faults is at least two orders of
magnitude smaller than the avalanche energy rating of
most MOSFETs, the peak current may exceed the avalanche
current rating of the MOSFET. In this case and if positive-
going transient energy from other external sources exceeds
the MOSFETs avalanche energy rating, add TVS clamps
across each MOSFET as shown in Figure6.
Externally applied input transients in the negative direc
-
tion are clamped by the body diodes of the MOSFETs to
700mV
with respect to V
OUT
, if not connected directly
through R
DS(ON)
to V
OUT
, and pose no particular hazard
for the DA and DB pins. Negative input transients couple
directly to the output which increases the RTN to V
OUT
voltage. Although the shunt resistor, R
Z
, limits the current
into V
Z
to a safe level of less than 10mA, an output capaci-
tor or TVS clamp may be required to protect downstream
circuitr
y from negative input transients.
100V BV
DSS(MIN)
MOSFETs are commonly used in –48V
applications, but BV
DSS(MAX)
is not guaranteed and cannot
be relied upon to protect the DA and DB pins from exceed-
ing their absolute maximum rating of 100V. Nevertheless,
the 100V
absolute maximum rating for DA and DB may
be safely exceeded if certain precautions are taken. The
internal
130V clamps shown in the Block Diagram tolerate
LTC4371
12
4371f
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Figure 7. 300V Drain Pin Protection
Figure 10. Drain Protection for Applications Up to –600V
4371 F07
LTC4371
DA GA SA V
SS
R
DA
20k
M1
V
A
V
OUT
Figure 9. High Voltage Drain Pin Protection with C1 and
R1 Maintaining Fast Turn-Off Time
4371 F08
LTC4371
DA GA SA V
SS
R
DA
100k
R1
10k
M1
V
A
V
OUT
C1
100pF
4371 F10
LTC4371
DA GA SA V
SS
M2
BSS127
M1
V
A
V
OUT
V
Z
R
Z
D1
IN4148W
Figure 8. Reverse Response Time vs. Drain Pin Resistance
V
DD
= 12.4V
∆V
SD
= 0.1V TO –0.4V
C
GATE
= 3.3nF
DRAIN PIN RESISTANCE (kΩ)
0
100
0
150
300
450
600
t
OFF
(ns)
Drain Pin Resistance
4371 F09
up to 10mA for 6ms in breakdown. For protection against
transients exceeding 100V, add series resistors R
DA
and
R
DB
according to:
R
DA
, R
DB
>
V
IN(PK)
V
BVD(MIN)
10mA
(8)
where V
IN(PK)
is the peak input voltage measured with
respect to V
SS
, and V
BVD(MIN)
is the minimum drain pin
breakdown voltage (100V).
Because their presence incurs no particular performance
penalty, a minimum value of 20k is prudent and pro
-
tects the DA and DB pins against transients up to 300V,
as shown in Figure7. A practical limit for R
DA
and R
DB
is 100k, beyond which their resistance interferes with
the operation of the gate amplifier. Some speed penalty
is incurred for values greater than 20k, as shown in
Figure 8. If the speed penalty is unacceptable, add a
resistor and capacitor across R
DA
and R
DB
as shown in
Figure9 to restore the response time.
High Voltage DC Applications
An extra blocking device is necessary to protect the DA
and DB pins in applications where the DC input voltage
exceeds 100V. Even in –48V applications the equivalent
DC input voltage may exceed 100V, as a result of a reverse
connected supply feed that can impress up to double the
maximum operating voltage across the inputs.
Because the 130V DA and DB pin clamps are limited to
clamping short-term spikes, some other means of limiting
the maximum applied voltage is necessary in DC applica
-
tions. The N-channel cascode shown in Figure10 extends
the DC input operating voltage to 600V
. It safely clamps
the drain pin to about 2V less than V
Z
, yet introduces only
500Ω series resistance when the input is in the vicinity of
V
OUT
; fast turn-off time is maintained.

LTC4371CMS#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Power Management Specialized - PMIC 2x Neg V Ideal Diode-OR Cntr & Mon
Lifecycle:
New from this manufacturer.
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