1SX250LH3F55I2LG Datasheet 1SX280LH3F55E2VG, 1SX280LH2F55E2VG, 1SX250LH2F55E1VG | P22-P24

1.11. 10G Ethernet Hard IP

Intel Stratix 10 devices include IEEE 802.3 10-Gbps Ethernet (10GbE) compliant

10GBASE-R PCS and PMA hard IP. The scalable 10GbE hard IP supports multiple

independent 10GbE ports while using a single PLL for all the 10GBASE-R PCS

instantiations, which saves on core logic resources and clock networks.

The integrated serial transceivers simplify multi-port 10GbE systems compared to 10

GbE Attachment Unit Interface (XAUI) interfaces that require an external XAUI-to-10G

PHY. Furthermore, the integrated transceivers incorporate signal conditioning circuits,

which enable direct connection to standard 10G XFP and SFP+ pluggable optical

modules. The transceivers also support backplane Ethernet applications and include a

hard 10GBASE-KR/40GBASE-KR4 Forward Error Correction (FEC) circuit that can be

used for both 10G and 40G applications. The integrated 10G Ethernet hard IP and 10G

transceivers save external PHY cost, board space and system power. The 10G Ethernet

PCS hard IP and 10GBASE-KR FEC are present in every transceiver channel.

1.12. External Memory and General Purpose I/O

Intel Stratix 10 devices offer substantial external memory bandwidth, with up to ten

72-bit wide DDR4 memory interfaces running at up to 2666 Mbps.

This bandwidth is provided along with the ease of design, lower power, and resource

efficiencies of hardened high-performance memory controllers. The external memory

interfaces can be configured up to a maximum width of 144 bits when using either

hard or soft memory controllers.

Figure 8. Hard Memory Controller

AXI/Avalon IF

Memory Controller

PHY Interface

Hard PHY

Hard Nios II

(Callibration/Control)

I/O Interface

ECCDQ/DQSCMD/ADDR

User Design

Core Fabric

Stratix 10 FPGA

Hard

Memory

Controller

1. Intel

Stratix

10 GX/SX Device Overview

S10-OVERVIEW | 2018.08.08

Stratix 10 GX/SX Device Overview

Each I/O bank contains 48 general purpose I/Os and a high-efficiency hard memory

controller capable of supporting many different memory types, each with different

performance capabilities. The hard memory controller is also capable of being

bypassed and replaced by a soft controller implemented in the user logic. The I/Os

each have a hardened double data rate (DDR) read/write path (PHY) capable of

performing key memory interface functionality such as:

• Read/write leveling

• FIFO buffering to lower latency and improve margin

• Timing calibration

• On-chip termination

The timing calibration is aided by the inclusion of hard microcontrollers based on

Intel’s Nios

II technology, specifically tailored to control the calibration of multiple

memory interfaces. This calibration allows the Intel Stratix 10 device to compensate

for any changes in process, voltage, or temperature either within the Intel Stratix 10

device itself, or within the external memory device. The advanced calibration

algorithms ensure maximum bandwidth and robust timing margin across all operating

conditions.

Table 10. External Memory Interface Performance

The listed speeds are for the 1-rank case.

Interface Controller Type Performance

DDR4 Hard 2666 Mbps

DDR3 Hard 2133 Mbps

QDRII+ Soft 1,100 Mtps

QDRII+ Xtreme Soft 1,266 Mtps

QDRIV Soft 2,133 Mtps

RLDRAM III Soft 2400 Mbps

RLDRAM II Soft 533 Mbps

In addition to parallel memory interfaces, Intel Stratix 10 devices support serial

memory technologies such as the Hybrid Memory Cube (HMC). The HMC is supported

by the Intel Stratix 10 high-speed serial transceivers, which connect up to four HMC

links, with each link running at data rates of 15 Gbps (HMC short reach specification).

Intel Stratix 10 devices also feature general purpose I/Os capable of supporting a wide

range of single-ended and differential I/O interfaces. LVDS rates up to 1.6 Gbps are

supported, with each pair of pins having both a differential driver and a differential

input buffer. This enables configurable direction for each LVDS pair.

1.13. Adaptive Logic Module (ALM)

Intel Stratix 10 devices use a similar adaptive logic module (ALM) as the previous

generation Arria 10 and Stratix V FPGAs, allowing for efficient implementation of logic

functions and easy conversion of IP between the devices.

The ALM block diagram shown in the following figure has eight inputs with a

fracturable look-up table (LUT), two dedicated embedded adders, and four dedicated

registers.

1. Intel

Stratix

10 GX/SX Device Overview

S10-OVERVIEW | 2018.08.08

Stratix 10 GX/SX Device Overview

Figure 9. Intel Stratix 10 FPGA and SoC ALM Block Diagram

Reg

4 Registers per ALM

Full

Adder

Full

Adder

Adaptive

LUT

Key features and capabilities of the ALM include:

• High register count with 4 registers per 8-input fracturable LUT, operating in

conjunction with the new HyperFlex architecture, enables Intel Stratix 10 devices

to maximize core performance at very high core logic utilization

• Implements select 7-input logic functions, all 6-input logic functions, and two

independent functions consisting of smaller LUT sizes (such as two independent 4-

input LUTs) to optimize core logic utilization

The Intel Quartus Prime software leverages the ALM logic structure to deliver the

highest performance, optimal logic utilization, and lowest compile times. The Intel

Quartus Prime software simplifies design reuse as it automatically maps legacy

designs into the Intel Stratix 10 ALM architecture.

1.14. Core Clocking

Core clocking in Intel Stratix 10 devices makes use of programmable clock tree

synthesis.

This technique uses dedicated clock tree routing and switching circuits, and allows the

Intel Quartus Prime software to create the exact clock trees required for your design.

Clock tree synthesis minimizes clock tree insertion delay, reduces dynamic power

dissipation in the clock tree and allows greater clocking flexibility in the core while still

maintaining backwards compatibility with legacy global and regional clocking schemes.

1. Intel

Stratix

10 GX/SX Device Overview

S10-OVERVIEW | 2018.08.08

Stratix 10 GX/SX Device Overview

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