Complex multiplication is very common in DSP algorithms. One of the most popular
applications of complex multipliers is the FFT algorithm. This algorithm has the
characteristic of increasing precision requirements on only one side of the multiplier.
The Variable Precision DSP block supports the FFT algorithm with proportional increase
in DSP resources as the precision grows.
Table 13. Complex Multiplication With Variable Precision DSP Block
Complex Multiplier
Size
DSP Block Resources FFT Usage
18x19 bits 2 Variable Precision DSP Blocks Resource optimized FFT
27x27 bits 4 Variable Precision DSP Blocks Highest precision FFT
For FFT applications with high dynamic range requirements, the Intel FFT IP Core
offers an option of single precision floating point implementation with resource usage
and performance similar to high precision fixed point implementations.
Other features of the DSP block include:
• Hard 18-bit and 25-bit pre-adders
• Hard floating point multipliers and adders
• 64-bit dual accumulator (for separate I, Q product accumulations)
• Cascaded output adder chains for 18- and 27-bit FIR filters
• Embedded coefficient registers for 18- and 27-bit coefficients
• Fully independent multiplier outputs
• Inferability using HDL templates supplied by the Intel Quartus Prime software for
most modes
The Variable Precision DSP block is ideal to support the growing trend towards higher
bit precision in high performance DSP applications. At the same time, it can efficiently
support the many existing 18-bit DSP applications, such as high definition video
processing and remote radio heads. With the Variable Precision DSP block architecture
and hard floating point multipliers and adders, Intel Stratix 10 devices can efficiently
support many different precision levels up to and including floating point
implementations. This flexibility can result in increased system performance, reduced
power consumption, and reduce architecture constraints on system algorithm
designers.
1.18. Hard Processor System (HPS)
The Intel Stratix 10 SoC Hard Processor System (HPS) is Intel’s industry leading third
generation HPS. Leveraging the performance of Intel’s 14-nm Tri-Gate technology,
Intel Stratix 10 SoC devices more than double the performance of previous generation
SoCs with an integrated quad-core 64-bit ARM Cortex-A53. The HPS also enables
system-wide hardware virtualization capabilities by adding a system memory
management unit. These architecture improvements ensure that Intel Stratix 10 SoCs
will meet the requirements of current and future embedded markets, including
wireless and wireline communications, data center acceleration, and numerous
military applications.
1. Intel
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Stratix
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10 GX/SX Device Overview
S10-OVERVIEW | 2018.08.08
Stratix 10 GX/SX Device Overview
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