1SX250LH3F55I2LG Datasheet 1SX280LH3F55E2VG, 1SX280LH2F55E2VG, 1SX250LH2F55E1VG | P31-P33

Feature Description

Communication Interface

Controllers

• Three 10/100/1000 Ethernet media access controls (MAC) with integrated DMA

— Supports RGMII and RMII external PHY Interfaces

— Option to support other PHY interfaces through FPGA logic

• GMII

• MII

• RMII (requires MII to RMII adapter)

• RGMII (requires GMII to RGMII adapter)

• SGMII (requires GMII to SGMII adapter)

— Supports IEEE 1588-2002 and IEEE 1588-2008 standards for precision networked

clock synchronization

— Supports IEEE 802.1Q VLAN tag detection for reception frames

— Supports Ethernet AVB standard

• Two USB On-the-Go (OTG) controllers with DMA

— Dual-Role Device (device and host functions)

• High-speed (480 Mbps)

• Full-speed (12 Mbps)

• Low-speed (1.5 Mbps)

• Supports USB 1.1 (full-speed and low-speed)

— Integrated descriptor-based scatter-gather DMA

— Support for external ULPI PHY

— Up to 16 bidirectional endpoints, including control endpoint

— Up to 16 host channels

— Supports generic root hub

— Configurable to OTG 1.3 and OTG 2.0 modes

• Five I

C controllers (three can be used by EMAC for MIO to external PHY)

— Support both 100Kbps and 400Kbps modes

— Support both 7-bit and 10-bit addressing modes

— Support Master and Slave operating mode

• Two UART 16550 compatible

— Programmable baud rate up to 115.2Kbaud

• Four serial peripheral interfaces (SPI) (2 Master, 2 Slaves)

— Full and Half duplex

Timers and I/O

• Timers

— 4 general-purpose timers

— 4 watchdog timers

• 48 HPS direct I/O allow HPS peripherals to connect directly to I/O

• Up to three IO48 banks may be assigned to HPS for HPS DDR access

Interconnect to Logic Core • FPGA-to-HPS Bridge

— Allows IP bus masters in the FPGA fabric to access to HPS bus slaves

— Configurable 32-, 64-, or 128-bit AMBA AXI interface

• HPS-to-FPGA Bridge

— Allows HPS bus masters to access bus slaves in FPGA fabric

— Configurable 32-, 64-, or 128-bit AMBA AXI interface allows high-bandwidth HPS

master transactions to FPGA fabric

• HPS-to-SDM and SDM-to-HPS Bridges

— Allows the HPS to reach the SDM block and the SDM to bootstrap the HPS

• Light Weight HPS-to-FPGA Bridge

— Light weight 32-bit AXI interface suitable for low-latency register accesses from HPS

to soft peripherals in FPGA fabric

• FPGA-to-HPS SDRAM Bridge

— Up to three AMBA AXI interfaces supporting 32, 64, or 128-bit data paths

1. Intel

Stratix

10 GX/SX Device Overview

S10-OVERVIEW | 2018.08.08

Stratix 10 GX/SX Device Overview

1.19. Power Management

Intel Stratix 10 devices leverage the advanced Intel 14-nm Tri-Gate process

technology, the all new HyperFlex core architecture to enable Hyper-Folding, power

gating, and several optional power reduction techniques to reduce total power

consumption by as much as 70% compared to previous generation high-performance

Stratix V devices.

Intel Stratix 10 standard power devices (-V) are SmartVID devices. The core voltage

supplies (VCC and VCCP) for each SmartVID device must be driven by a PMBus

voltage regulator dedicated to that Intel Stratix 10 device. Use of a PMBus voltage

regulator for each SmartVID (-V) device is mandatory; it is not an option. A code is

programmed into each SmartVID device during manufacturing that allows the PMBus

voltage regulator to operate at the optimum core voltage to meet the device

performance specifications.

With the new HyperFlex core architecture, designs can run 2X faster than previous

generation FPGAs. With 2X performance and same required throughput, architects can

cut the data path width in half to save power. This optimization is called Hyper-

Folding. Additionally, power gating reduces static power of unused resources in the

FPGA by powering them down. The Intel Quartus Prime software automatically powers

down specific unused resource blocks such as DSP and M20K blocks, at configuration

time.

The optional power reduction techniques in Intel Stratix 10 devices include:

• Available Low Static Power Devices—Intel Stratix 10 devices are available with

a fixed core voltage that provides lower static power than the SmartVID standard

power devices, while maintaining device performance

Furthermore, Intel Stratix 10 devices feature Intel’s industry-leading low power

transceivers and include a number of hard IP blocks that not only reduce logic

resources but also deliver substantial power savings compared to soft

implementations. In general, hard IP blocks consume up to 50% less power than the

equivalent soft logic implementations.

1.20. Device Configuration and Secure Device Manager (SDM)

All Intel Stratix 10 devices contain a Secure Device Manager (SDM), which is a

dedicated triple-redundant processor that serves as the point of entry into the device

for all JTAG and configuration commands. The SDM also bootstraps the HPS in SoC

devices ensuring that the HPS can boot using the same security features that the

FPGA devices have.

1. Intel

Stratix

10 GX/SX Device Overview

S10-OVERVIEW | 2018.08.08

Stratix 10 GX/SX Device Overview

Figure 14. SDM Block Diagram

Secure Device Manager

(SDM)

Dedicated Config I/O

FPGA

Sector

LSM

FPGA

Sector

LSM

FPGA

Sector

LSM

FPGA

Sector

LSM

Dual Purpose I/O

Configuration

Network

Customizable secure boot process

Private, public, and PUF-based

key support

Security Features

Interface bus used to transport

configuration data from SDM

throughout FPGA

Sectors can be selectively

configured and cleared of

sensitive parameters

Sectors configured in parallel

to reduce configuration time

LSM: Local Sector Manager

PUF: Physically Unclonable Function

During configuration, Intel Stratix 10 devices are divided into logical sectors, each of

which is managed by a local sector manager (LSM). The SDM passes configuration

data to each of the LSMs across the on-chip configuration network. This allows the

sectors to be configured independently, one at a time, or in parallel. This approach

achieves simplified sector configuration and reconfiguration, as well as reduced overall

configuration time due to the inherent parallelism. The same sector-based approach is

used to respond to single-event upsets and security attacks.

While the sectors provide a logical separation for device configuration and

reconfiguration, they overlay the normal rows and columns of FPGA logic and routing.

This means there is no impact to the Intel Quartus Prime software place and route,

and no impact to the timing of logic signals that cross the sector boundaries.

1. Intel

Stratix

10 GX/SX Device Overview

S10-OVERVIEW | 2018.08.08

Stratix 10 GX/SX Device Overview

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1SX250LH3F55I2LG

Mfr. #:

Buy 1SX250LH3F55I2LG

Manufacturer:

Intel / Altera

Description:

FPGA - Field Programmable Gate Array

Lifecycle:

New from this manufacturer.

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1SX250LH3F55I2LG

1SX250LH3F55I2LG

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