Document
Version
Changes
• Changed the features listed in the "Key Features of Stratix 10 Devices Compared to Stratix V
Devices" table.
• Changed the descriptions of the following areas of the "Stratix 10 FPGA and SoC Common Device
Features" table:
— Transceiver hard IP
— Internal memory blocks
— Core clock networks
— Packaging
• Reorganized and updated all tables in the "Stratix 10 FPGA and SoC Family Plan" section.
• Removed the "Migration Between Arria 10 FPGAs and Stratix 10 FPGAs" section.
• Removed footnotes from the "Transceiver PCS Features" table.
• Changed the HMC description in the "External Memory and General Purpose I/O" section.
• Changed the number of fPLLs in the "Fractional Synthesis PLLs and I/O PLLs" section.
• Clarified HMC data width support in the "Key Features of the Stratix 10 HPS" table.
• Changed the description in the "Internal Embedded Memory" section.
• Changed the datarate for the Standard PCS and SDI PCS features in the "Transceiver PCS Features"
table.
• Added a note to the "PCI Express Gen1/Gen2/Gen3 Hard IP" section.
• Updated the "Key Features of the Stratix 10 HPS" table.
• Changed the description for the Cache coherency unit in the "Key Features of the Stratix 10 HPS"
table.
• Changed the description for the external SDRAM and Flash memory interfaces for HPS in the "Key
Features of the Stratix 10 HPS" table.
2015.12.04 Initial release.
1. Intel
®
Stratix
®
10 GX/SX Device Overview
S10-OVERVIEW | 2018.08.08
Stratix 10 GX/SX Device Overview
37
