Dedicated secure device manager (SDM) for:
Enhanced device configuration and security
AES-256, SHA-256/384 and ECDSA-256/384 encrypt/decrypt accelerators and
authentication
Multi-factor authentication
Physically Unclonable Function (PUF) service and software programmable
device configuration capability
Comprehensive set of advanced power saving features delivering up to 70% lower
power compared to previous generation high-performance FPGAs
Non-destructive register state readback and writeback, to support ASIC
prototyping and other applications
With these capabilities, Intel Stratix 10 FPGAs and SoCs are ideally suited for the most
demanding applications in diverse markets such as:
Compute and Storage—for custom servers, cloud computing and data center
acceleration
Networking—for Terabit, 400G and multi-100G bridging, aggregation, packet
processing and traffic management
Optical Transport Networks—for OTU4, 2xOTU4, 4xOTU4
Broadcast—for high-end studio distribution, headend encoding/decoding, edge
quadrature amplitude modulation (QAM)
Military—for radar, electronic warfare, and secure communications
Medical—for diagnostic scanners and diagnostic imaging
Test and Measurement—for protocol and application testers
Wireless—for next-generation 5G networks
ASIC Prototyping—for designs that require the largest monolithic FPGA fabric
with the highest I/O count
1.1. Intel Stratix 10 Family Variants
Intel Stratix 10 devices are available in FPGA (GX) and SoC (SX) variants.
Intel Stratix 10 GX devices deliver up to 1 GHz core fabric performance and
contain up to 5.5 million LEs in a monolithic fabric. They also feature up to 96
general purpose transceivers on separate transceiver tiles, and 2666 Mbps DDR4
external memory interface performance. The transceivers are capable of up to
28.3 Gbps short reach and across the backplane. These devices are optimized for
FPGA applications that require the highest transceiver bandwidth and core fabric
performance, with the power efficiency of Intel’s industry-leading 14-nm Tri-Gate
process technology.
Intel Stratix 10 SX devices have a feature set that is identical to Intel Stratix 10
GX devices, with the addition of an embedded quad-core 64-bit ARM Cortex A53
hard processor system.
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Common to all Intel Stratix 10 family variants is a high-performance fabric based on
the new HyperFlex core architecture that includes additional Hyper-Registers
throughout the interconnect routing and at the inputs of all functional blocks. The core
fabric also contains an enhanced logic array utilizing Intel’s adaptive logic module
(ALM) and a rich set of high performance building blocks including:
M20K (20 kbit) embedded memory blocks
Variable precision DSP blocks with hard IEEE 754 compliant floating-point units
Fractional synthesis and integer PLLs
Hard memory controllers and PHY for external memory interfaces
General purpose IO cells
To clock these building blocks, Intel Stratix 10 devices use programmable clock tree
synthesis, which uses dedicated clock tree routing to synthesize only those branches
of the clock trees required for the application. All devices support in-system, fine-
grained partial reconfiguration of the logic array, allowing logic to be added and
subtracted from the system while it is operating.
All family variants also contain high speed serial transceivers, containing both the
physical medium attachment (PMA) and the physical coding sublayer (PCS), which can
be used to implement a variety of industry standard and proprietary protocols. In
addition to the hard PCS, Intel Stratix 10 devices contain multiple instantiations of PCI
Express hard IP that supports Gen1/Gen2/Gen3 rates in x1/x2/x4/x8/x16 lane
configurations, and hard 10GBASE-KR/40GBASE-KR4 FEC for every transceiver. The
hard PCS, FEC, and PCI Express IP free up valuable core logic resources, save power,
and increase your productivity.
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1.1.1. Available Options
Figure 1. Sample Ordering Code and Available Options for Intel Stratix 10 Devices
Family Signature
Transceiver Count
Transceiver
Speed Grade
Package Type
Package Code
Operating Temperature
FPGA Fabric
Speed Grade
Optional Suffix
Indicates specific device
options or shipment method
G : GX variant
28.3 Gbps transceivers
1S : Stratix 10
040
: 400K logic elements
U : 96
H : 24
N : 48
3
1 (fastest)
2
F : FineLine BGA (FBGA), 1.0 mm pitch
FBGA Package Type
35 : 1,152 pins, 35 mm x 35 mm
43 : 1,760 pins, 42.5 mm x 42.5 mm
48 : 2,112 pins, 47.5 mm x 47.5 mm
50 : 2,397 pins, 50 mm x 50 mm
55 : 2,912 pins, 55 mm x 55 mm
I
: Industrial (T
J
= -40° C to 100° C)
E : Extended (T
J
= 0° C to 100° C)
1 (fastest)
2
3
Power Option
V : SmartVID standard power
L
:
Low Power (Fixed Voltage)
RoHS
G : RoHS6
P
:
Leaded (1)
S<n> : Engineering sample
1S
G F
280
N
2
V35 I
2
S1G
Logic Density
Family Variant
X : Extreme Low Power (Fixed Voltage)
X : SX variant
28.3 Gbps transceivers
ARM A53 processor
065 : 650K logic elements
085 : 850K logic elements
110 : 1,100K logic elements
165 : 1,650K logic elements
210 : 2,100K logic elements
250 : 2,500K logic elements
280 : 2,800K logic elements
450 : 4,500K logic elements
550 : 5,500K logic elements
L
SiP Code
L : L-Tile
H : H-Tile
Note:
1. Contact Intel for availability
1.2. Innovations in Intel Stratix 10 FPGAs and SoCs
Intel Stratix 10 FPGAs and SoCs deliver many significant improvements over the
previous generation high-performance Stratix V FPGAs.
Table 1. Key Features of Intel Stratix 10 Devices Compared to Stratix V Devices
Feature Stratix V FPGAs Intel Stratix 10 FPGAs and SoCs
Process technology 28-nm TSMC (planar
transistor)
14 nm Intel Tri-Gate (FinFET)
Hard processor core None Quad-core 64-bit ARM Cortex-A53
(SoC only)
Core architecture Conventional core architecture
with conventional interconnect
HyperFlex core architecture with
Hyper-Registers in the interconnect
Core performance 500 MHz 1 GHz
Power dissipation 1x As low as 0.3x
continued...
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1SX250LH3F55I2LG

Mfr. #:
Manufacturer:
Intel / Altera
Description:
FPGA - Field Programmable Gate Array
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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