COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
4
©
Figure 1. Output Load
*includes jig and scope capacitances
or equivalent circuit
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C)
Commercial Com'l & Ind'l
(1)
Com'l & Ind'l
(1)
IDT72421L10 IDT72421L15 IDT72421L25
IDT72201L10 IDT72201L15 IDT72201L25
IDT72211L10 IDT72211L15 IDT72211L25
IDT72221L10 IDT72221L15 IDT72221L25
IDT72231L10 IDT72231L15 IDT72231L25
IDT72241L10 IDT72241L15 IDT72241L25
IDT72251L10 IDT72251L15 IDT72251L25
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
fS Clock Cycle Frequency 100 66.7 40 MHz
tA Data Access Time 2 6.5 2 10 2 15 ns
tCLK Clock Cycle Time 10 15 25 ns
tCLKH Clock High Time 4.5 6 10 ns
tCLKL Clock Low Time 4.5 6 10 ns
tDS Data Setup Time 3 4 6 ns
tDH Data Hold Time 0.5 1 1 ns
tENS Enable Setup Time 3 4 6 ns
tENH Enable Hold Time 0.5 1 1 ns
tRS Reset Pulse Width
(2)
10 15 15 ns
tRSS Reset Setup Time 8 10 15 ns
tRSR Reset Recovery Time 8 10 15 ns
tRSF Reset to Flag and Output Time 10 15 25 ns
tOLZ Output Enable to Output in Low-Z
(3)
0— 0 0 ns
tOE Output Enable to Output Valid 3 6 3 8 3 13 ns
tOHZ Output Enable to Output in High-Z
(3)
36 38 313ns
tWFF Write Clock to Full Flag 6.5 10 15 ns
tREF Read Clock to Empty Flag 6.5 10 15 ns
tPAF Write Clock to Programmable Almost-Full Flag 6.5 10 15 ns
tPAE Read Clock to Programmable Almost-Empty Flag 6.5 10 15 ns
tSKEW1 Skew time between Read Clock & Write Clock for 5 6 10 ns
Empty Flag & Full Flag
tSKEW2 Skew time between Read Clock & Write Clock for 14 15 18 ns
Almost-Empty Flag & Programmable Almost-Full Flag
NOTES:
1. Industrial temperature range product for the 15ns and 25ns speed grades are available as standard product.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
In Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure 1
CAPACITANCE (Ta = +25°C, f = 1.0MHz)
Symbol Parameter Conditions Max. Unit
CIN
(2)
Input Capacitance VIN = 0V 10 pF
C
OUT
(1,2)
Output Capacitance VOUT = 0V 10 pF
30pF*
1.1K
5V
680Ω
D.U.T.
2655 drw 03
NOTES:
1. With output deselected (OE VIH).
2. Characterized values, not currently tested.
AC TEST CONDITIONS
5
©
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
OUTPUT ENABLE (OE)
When Output Enable (OE) is enabled (LOW), the parallel output buffers
receive data from the output register. When Output Enable (OE) is disabled
(HIGH), the Q output data bus is in a high-impedance state.
WRITE ENABLE 2/LOAD (WEN2/LD)
This is a dual-purpose pin. The FIFO is configured at Reset to have
programmable flags or to have two write enables, which allows depth expansion.
If Write Enable 2/Load (WEN2/LD) is set HIGH at Reset (RS = LOW), this pin
operates as a second write enable pin.
If the FIFO is configured to have two write enables, when Write Enable
(WEN1) is LOW and Write Enable 2/Load (WEN2/LD) is HIGH, data can be
loaded into the input register and RAM array on the LOW-to-HIGH transition
of every Write Clock (WCLK). Data is stored in the RAM array sequentially and
independently of any ongoing read operation.
In this configuration, when Write Enable (WEN1) is HIGH and/or Write
Enable 2/Load (WEN2/LD) is LOW, the input register holds the previous data
and no new data is allowed to be loaded into the register.
To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further
write operations. Upon the completion of a valid read cycle, the Full Flag (FF)
will go HIGH after t
WFF, allowing a valid write to begin. Write Enable 1 (WEN1)
and Write Enable 2/Load (WEN2/LD) are ignored when the FIFO is full.
The FIFO is configured to have programmable flags when the Write Enable
2/Load (WEN2/LD) is set LOW at Reset (RS=LOW). The IDT72421/72201/
72211/72221/72231/72241/72251 devices contain four 8-bit offset registers
which can be loaded with data on the inputs, or read on the outputs. See Figure
3 for details of the size of the registers and the default values.
If the FIFO is configured to have programmable flags when the Write Enable
1 (WEN1) and Write Enable 2/Load (WEN2/LD) are set LOW, data on the inputs
D is written into the Empty (Least Significant Bit) Offset register on the first LOW-
to-HIGH transition of the Write Clock (WCLK). Data is written into the Empty (Most
Significant Bit) Offset register on the second LOW-to-HIGH transition of the Write
Clock (WCLK), into the Full (Least Significant Bit) Offset register on the third
transition, and into the Full (Most Significant Bit) Offset register on the fourth
transition. The fifth transition of the Write Clock (WCLK) again writes to the Empty
(Least Significant Bit) Offset register.
However, writing all offset registers does not have to occur at one time. One
or two offset registers can be written and then by bringing the Write Enable 2/
Load (WEN2/LD) pin HIGH, the FIFO is returned to normal read/write
operation. When the Write Enable 2/Load (WEN2/LD) pin is set LOW, the Write
Enable 1 (WEN1) is LOW, the next offset register in sequence is written.
SIGNAL DESCRIPTIONS
INPUTS:
DATA IN (D0 - D8)
Data inputs for 9-bit wide data.
CONTROLS:
RESET (RS)
Reset is accomplished whenever the Reset (RS) input is taken to a LOW
state. During reset, both internal read and write pointers are set to the first
location. A reset is required after power-up before a write operation can take
place. The Full Flag (FF) and Programmable Almost-Full flag (PAF) will be reset
to HIGH after t
RSF. The Empty Flag (EF) and Programmable Almost-Empty
flag (PAE) will be reset to LOW after tRSF. During reset, the output register is
initialized to all zeros and the offset registers are initialized to their default values.
WRITE CLOCK (WCLK)
A write cycle is initiated on the LOW-to-HIGH transition of the Write Clock
(WCLK). Data setup and hold times must be met in respect to the LOW-to-HIGH
transition of WCLK. The Full Flag (FF) and Programmable Almost-Full flag
(PAF) are synchronized with respect to the LOW-to-HIGH transition of WCLK.
The Write and Read Clocks can be asynchronous or coincident.
WRITE ENABLE 1 (WEN1)
If the FIFO is configured for programmable flags, Write Enable 1 (WEN1)
is the only enable control pin. In this configuration, when Write Enable 1 (WEN1)
is LOW, data can be loaded into the input register and RAM array on the LOW-
to-HIGH transition of every Write Clock (WCLK). Data is stored in the RAM array
sequentially and independently of any ongoing read operation.
In this configuration, when Write Enable 1 (WEN1) is HIGH, the input register
holds the previous data and no new data is allowed to be loaded into the register.
If the FIFO is configured to have two write enables, which allows for depth
expansion, there are two enable control pins. See Write Enable 2 paragraph
below for operation in this configuration.
To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further
write operations. Upon the completion of a valid read cycle, the Full Flag (FF)
will go HIGH after tWFF, allowing a valid write to begin. Write Enable 1 (WEN1)
is ignored when the FIFO is full.
READ CLOCK (RCLK)
Data can be read on the outputs on the LOW-to-HIGH transition of the Read
Clock (RCLK). The Empty Flag (EF) and Programmable Almost-Empty flag
(PAE) are synchronized with respect to the LOW-to-HIGH transition of RCLK.
The Write and Read Clocks can be asynchronous or coincident.
READ ENABLES (REN1, REN2)
When both Read Enables (REN1, REN2) are LOW, data is read from the
RAM array to the output register on the LOW-to-HIGH transition of the Read
Clock (RCLK).
When either Read Enable (REN1, REN2) is HIGH, the output register holds
the previous data and no new data is allowed to be loaded into the register.
When all the data has been read from the FIFO, the Empty Flag (EF) will
go LOW, inhibiting further read operations. Once a valid write operation has
been accomplished, the Empty Flag (EF) will go HIGH after tREF and a valid
read can begin. The Read Enables (REN1, REN2) are ignored when the FIFO
is empty.
LD WEN1 WCLK Selection
0 0 Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
0 1 No Operation
1 0 Write Into FIFO
1 1 No Operation
NOTE:
1. For the purposes of this table, WEN2 = VIH.
2. The same selection sequence applies to reading from the registers. REN1 and REN2
are enabled and read is performed on the LOW-to-HIGH transition of RCLK.
Figure 2. Write Offset Register
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
6
©
Figure 3. Offset Register Location and Default Values
86 0
Empty Offset (LSB) Reg.
Default Value 007H
80
Full Offset (LSB) Reg.
Default Value 007H
87 0
Empty Offset (LSB) Reg.
Default Value 007H
80
Full Offset (LSB) Reg.
Default Value 007H
7
80
Empty Offset (LSB)
Default Value 007H
80
Full Offset (LSB)
Default Value 007H
IDT72421 - 64 x 9-BIT IDT72201 - 256 x 9-BIT
IDT72211 - 512 x 9-BIT
7
7
80
(MSB)
1
80
0
0
80
87 0
Empty Offset (LSB) Reg.
Default Value 007H
80
Full Offset (LSB) Reg.
Default Value 007H
7
87 0
Empty Offset (LSB) Reg.
Default Value 007H
80
Empty Offset (LSB)
Default Value 007H
IDT72221 - 1,024 x 9-BIT
IDT72231 - 2,048 x 9-BIT
IDT72241 - 4,096 x 9-BIT
7
8080
(MSB)
0000
2
(MSB)
000
3
80
(MSB)
00
1
80
(MSB)
00
1
5
65
80
8
0
8
(MSB)
1
0
IDT72251 8,192 x 9-BIT
80
Empty Offset (LSB)
Default Value 007H
7
80
(MSB)
00000
4
87 0
Full Offset (LSB) Reg.
Default Value 007H
802
(MSB)
000
80
Full Offset (LSB)
Default Value 007H
7
80
(MSB)
0000
3
80
Full Offset (LSB)
Default Value 007H
7
80
(MSB)
00000
4
2655 drw 05
The contents of the offset registers can be read on the output lines when the
Write Enable 2/Load (WEN2/LD) pin is set LOW and both Read Enables (REN1,
REN2) are set LOW. Data can be read on the LOW-to-HIGH transition of the
Read Clock (RCLK).
A read and write should not be performed simultaneously to the offset
registers.

72251L15PFGI

Mfr. #:
Manufacturer:
IDT
Description:
FIFO 8K X 9 SYNCFIFO
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union