7
©
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
OUTPUTS:
FULL FLAG (FF)
The Full Flag (FF) will go LOW, inhibiting further write operation, when the
device is full. If no reads are performed after Reset (RS), the Full Flag (FF)
will go LOW after 64 writes for the IDT72421, 256 writes for the IDT72201, 512
writes for the IDT72211, 1,024 writes for the IDT72221, 2,048 writes for the
IDT72231, 4,096 writes for the IDT72241, and 8,192 writes for the IDT72251.
The Full Flag (FF) is synchronized with respect to the LOW-to-HIGH
transition of the Write Clock (WCLK).
EMPTY FLAG (EF)
The Empty Flag (EF) will go LOW, inhibiting further read operations, when
the read pointer is equal to the write pointer, indicating the device is empty.
The Empty Flag (EF) is synchronized with respect to the LOW-to-HIGH
transition of the Read Clock (RCLK).
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
reaches the almost-full condition. If no reads are performed after Reset (RS),
the Programmable Almost-Full flag (PAF) will go LOW after (64-m) writes for the
IDT72421, (256-m) writes for the IDT72201, (512-m) writes for the IDT72211,
TABLE 1 — STATUS FLAGS
NUMBER OF WORDS IN FIFO
IDT72421 IDT72201 IDT72211 FF PAF PA E EF
000HHLL
1 to n 1 to n 1 to n H H L H
(n+1) to (64-(m+1)) (n+1) to (256-(m+1)) (n+1) to (512-(m+1)) H H H H
(64-m)
(2)
to 63 (256-m)
(2)
to 255 (512-m)
(2)
to 511 H L H H
64 256 512 L L H H
NUMBER OF WORDS IN FIFO
IDT72221 IDT72231 IDT72241 IDT72251 FF PAF PA E EF
00 0 0HHLL
1 to n
(1)
1 to n
(1)
1 to n
(1)
1 to n
(1)
HH LH
(n+1) to (1,024-(m+1)) (n+1) to (2,048-(m+1)) (n+1) to (4,096-(m+1)) (n+1) to (8,192-(m+1)) H H H H
(1,024-m)
(2)
to 1,023 (2,048-m)
(2)
to 2,047 (4,096-m)
(2)
to 4,095 (8,192-m)
(2)
to 8,191 H L H H
1,024 2,048 4,096 8,192 L L H H
NOTES:
1. n = Empty Offset (n = 7 default value)
2. m = Full Offset (m = 7 default value)
(1,024-m) writes for the IDT72221, (2,048-m) writes for the IDT72231, (4,096-
m) writes for the IDT72241, and (8,192-m) writes for the IDT72251. The offset
“m” is defined in the Full offset registers.
If there is no Full offset specified, the Programmable Almost-Full flag (PAF)
will go LOW at Full-7 words.
The Programmable Almost-Full flag (PAF) is synchronized with respect to
the LOW-to-HIGH transition of the Write Clock (WCLK).
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
The Programmable Almost-Empty flag (PAE) will go LOW when the read
pointer is "n+1" locations less than the write pointer. The offset "n" is defined
in the Empty Offset registers. If no reads are performed after Reset the
Programmable Almost-Empty flag (PAE) will go HIGH after "n+1" for the
IDT72421/72201/72211/72221/72231/72241/72251.
If there is no Empty offset specified, the Programmable Almost-Empty flag
(PAE) will go LOW at Empty+7 words.
The Programmable Almost-Empty flag (PAE) is synchronized with respect
to the LOW-to-HIGH transition of the Read Clock (RCLK).
DATA OUTPUTS (Q0 - Q8)
Data outputs for a 9-bit wide data.
(1) (1) (1)
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
8
©
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between the rising edge of RCLK
and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
Figure 5. Write Cycle Timing
NOTES:
1. Holding WEN2/LD HIGH during reset will make the pin act as a second write enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmable
flag offset registers.
2. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.
3. The clocks (RCLK, WCLK) can be free-running during reset.
Figure 4. Reset Timing
t
RS
t
RSR
RS
REN1, REN2
t
RSF
t
RSF
OE = 1
OE = 0
(2)
EF, PAE
FF, PAF
Q
0
- Q
8
2655 drw 06
WEN1
(1)
WEN2/LD
t
RSS
t
RSF
t
RSR
t
RSS
t
RSR
t
RSS
t
DH
t
ENH
t
SKEW1
(1)
t
CLK
t
CLKH
t
CLKL
t
DS
t
ENS
t
WFF
t
WFF
WCLK
D
0
- D
8
WEN1
WEN2/
(If Applicable)
FF
RCLK
REN1,
REN2
NO OPERATION
NO OPERATION
2655 drw 07
DATA IN VALID
t
ENH
t
ENS
9
©
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
tDS
D0 (First Valid Write)
t
SKEW1
D0 D1
D3D2D1
tFRL
(1)
tREF
tA
tOLZ
tOE
tA
WCLK
D
0 - D8
WEN2
(If Applicable)
RCLK
EF
REN1,
REN2
Q
0 - Q8
OE
WEN1
2655 drw 09
tENS
tENS
tENS
NOTE:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between the rising edge of RCLK
and the rising edge of WCLK is less than tSKEW1, then EF may not change state until the next RCLK edge.
Figure 6. Read Cycle Timing
NOTE:
1. When tSKEW1 minimum specification, tFRL = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EF = LOW).
Figure 7. First Data Word Latency Timing
t
ENH
t
ENS
NO OPERATION
t
OLZ
VALID DATA
t
SKEW1
(1)
t
CLK
t
CLKH
t
CLKL
t
REF
t
REF
t
A
t
OE
t
OHZ
RCLK
REN1,
REN2
EF
Q
0
- Q
8
OE
WCLK
WEN1
WEN2
2655 drw 08

72251L15PFGI

Mfr. #:
Manufacturer:
IDT
Description:
FIFO 8K X 9 SYNCFIFO
Lifecycle:
New from this manufacturer.
Delivery:
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