ISL6730A, ISL6730B, ISL6730C, ISL6730D
16
FN8258.1
August 8, 2013
INPUT VOLTAGE SETTING
First, set the BO resistor divider gain, K
BO
according to
Equations 1 and 2.
Assuming the converter starts at V
LINE
= 80V
RMS
, then the BO
resistor divider gain, K
BO
should be:
In this design, two 3.3M resistors in series are used for R
IN2
.
So, R
IN1
is calculated:
Using resistor from the standard value, R
IN1
= 43k, the actual
K
BO
is calculated:
NEGATIVE INPUT CAPACITOR GENERATION
The ISL6730A, ISL6730B, ISL6730C, ISL6730D generates an
equivalent negative capacitance at the input to cancel the input
filter capacitance. Thus, more input capacitors can be used
without reducing the power factor.
The input equivalent negative capacitance is a function of the
current sensing gain, BO resistor divider gain and the
compensation components.
This equivalent negative capacitor cancels the input filter
capacitor required for EMI filtering. Therefore, the displacement
power factor significantly improves.
For example, C
F2
= 0.68µF, C
F1
= 0.94µF, using the low cost EMI
filter shown in Figure 13. When V
LINE
= 230VAC, f
LINE
= 50Hz,
P
O
= 60W.
Assuming 95% efficiency under the above test condition, the
resistive component, which is in phase to voltage:
The reactive current through the input capacitors:
Thus, the displacement power factor is:
The reactive current generated by the equivalent negative
capacitor is:
With the equivalent negative capacitor, the total reactive current
reduces to:
The displacement power factor increases to:
VOLTAGE LOOP COMPENSATION
The average diode forward current can be approximated by:
Assuming the input current traces the input voltage perfectly. The
input power is in proportion to (V
COMP
- 1V).
Where Δ
COMP
is the V
COMP
- 1V. 1V is the offset voltage.
R
IS
is the internal current scaling resistor. R
IS
= 14.2kΩ.
FIGURE 17. BODE PLOT OF THE ACTUAL CURRENT LOOP GAIN
-20
0
20
40
60
80
GAIN (dB)
10 100
1x10
3
0
45
90
135
180
FREQUENCY (Hz)
PHASE (°)
45
60
10.5kHz
1x10
3
1x10
3
10.5kHz
K
BO
0.5V
80V 2V
------------------------
0.00641==
(EQ. 57)
R
IN1
0.00641
1 0.00641
------------------------------ -
6.6MΩ() 42.6kΩ==
(EQ. 58)
K
BO
R
IN1
R
IN1
R
IN2
+
---------------------------------
0.00647==
(EQ. 59)
C
NEG
K
BO
0.8
V
m
V
OUT
----------------
⎝⎠
⎜⎟
⎛⎞
R
SEN
R
CS
A
iDC
--------------------------
C
ic
C
ip
+()=
(EQ. 60)
C
NEG
0.00647 0.8
1.5
390
--------- -
⎝⎠
⎛⎞
3.16k
0.068 1.9
---------------------------
18nF 1.2nF+()= 0.62μF=
(EQ. 61)
I
a
P
o
V
LINE
0.95
---------------------------------
= 0.275A=
(EQ. 62)
I
c
V
LINE
2π f
LINE
() C
F1
C
F2
+()= 0.117A=
(EQ. 63)
PF
DIS
I
a
I
a
()
2
I
c
()
2
+
-----------------------------------
= 0.92=
(EQ. 64)
I
cneg
V
LINE
2π f
LINE
() C
NEG
()= 0.045A=
(EQ. 65)
I
c
I
cneg
0.072A=
(EQ. 66)
PF
DIS
I
a
I
a
()
2
I
c
I
cneg
()
2
+
--------------------------------------------------------
= 0.967=
(EQ. 67)
I
Dave()
P
in
V
OUT
----------------
=
(EQ. 68)
I
Dave()
R
SEN
R
CS
0.5 R
IS
---------------------------------------
1
V
OUT
----------------
0.25
22()π()
2
K
BO
------------------------------------------------
⎝⎠
⎜⎟
⎜⎟
⎛⎞
Δ
COMP
=
(EQ. 69)
I
Dave()
0.598
A
V
--- -
Δ
COMP
=
(EQ. 70)
ISL6730A, ISL6730B, ISL6730C, ISL6730D
17
FN8258.1
August 8, 2013
Thus, the transfer function from V
COMP
to V
OUT
is:
As shown in Figure 18, the voltage loop gain is:
The output feedback resistor divider gain, G
DIV
is:
The compensation gain uses external impedance networks as
shown in Figure 18, Z
COMP
(s) is given by:
The targeted cross over frequency, F
CV
is 8Hz. The high frequency
pole, F
Pv
is required in order to reject the 2 time line frequency
component. F
Pv
= 20Hz. The targeted phase margin is 60°.
The zero, F
Zv
is calculated:
Then the total capacitance used for compensation is calculated:
Thus, the total compensation capacitance is:
Choose components from the standard values. We have
C
VP
= 100nF, C
VC
= 1500nF, R
VC
= 82.5k. The actual bode plot
is shown in Figure 20.
FB
COMP
Gmv
I
FB
2.5V
R
FB1
R
FB2
VOUT
FIGURE 18. OUTPUT VOLTAGE SENSING AND COMPENSATION
Rvc
Cvc
Cvp
G
PS
s()
V
OUT
s()
Δ
COMP
------------------------
=
1
C
O
s
----------------
I
Dave()
Δ
COMP
--------------------
=
(EQ. 71)
G
PS
s()
I
Dave()
C
O
s
-------------------
1
Δ
COMP
--------------------
⎝⎠
⎜⎟
⎛⎞
=
0.598
C
O
s
----------------
=
(EQ. 72)
G
VLOOP
s() G
PS
s() G
DIV
gmv Z
COMP
s()=
(EQ. 73)
G
DIV
V
REF
V
OUT
----------------
=
(EQ. 74)
Z
COMP
s()
1
C
vc
C
vp
+()s
---------------------------------------
R
vc
C
vc
s1+
R
vc
C
vc
C
vp
C
vc
C
vp
+
------------------------------------------
s 1+
------------------------------------------------------------ -
=
(EQ. 75)
100
80
60
40
20
0
-20
-40
-60
F
Pv
1k100101
F
Zv
GAIN (dB)
FREQUENCY (Hz)
FIGURE 19. ASYMPTOTIC BODE PLOT OF CURRENT LOOP GAIN
F
CV
G
PS
(s)
Gmv*Z
COMP
(s)
G
VLOOP
(s)
G
DIV
F
Zv
F
CV
Φ
m
F
CV
F
Pv
()()atan+()tan
------------------------------------------------------------------------------
=
(EQ. 76)
F
Zv
8Hz
60deg 8Hz()20Hz()()atan+()tan
------------------------------------------------------------------------------------------------
1.15Hz==
(EQ. 77)
C
vc
C
vp
+
G
PS
i2πF
CV
()()G
DIV
Gmv
2πF
CV
()
-------------------------------------------------------------------------------------------
F
CV
F
ZV
()
2
1+
F
CV
F
PV
()
2
1+
--------------------------------------------=
(EQ. 78)
C
vc
C
vp
+ 1829nF=
(EQ. 79)
C
vp
1829nF
F
ZV
F
PV
-----------
105nF==
(EQ. 80)
C
vc
1829nF 105nF 1724nF==
(EQ. 81)
R
vc
1
2 π F
ZV
C
VC
⋅⋅ ⋅
-------------------------------------------
81.2kΩ==
(EQ. 82)
FIGURE 20. BODE PLOT OF THE ACTUAL VOLTAGE LOOP GAIN
-40
-20
0
20
40
60
GAIN (dB)
0
1 10 100
1x10
3
0
15
30
45
60
75
90
FREQUENCY (Hz)
PHASE (deg)
ISL6730A, ISL6730B, ISL6730C, ISL6730D
18
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FN8258.1
August 8, 2013
For additional products, see www.intersil.com/en/products.html
About Intersil
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE REVISION CHANGE
August 8, 2013 FN8258.1 Added electronic specifications to parts ISL6730B/D and made necessary changes throughout document.
February 26, 2013 FN8258.0 Initial Release.

ISL6730DFUZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Power Factor Correction - PFC PFC Controller
Lifecycle:
New from this manufacturer.
Delivery:
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