XC2C128-7CPG132C Datasheet XC2C128-7CP132C, XC2C128-7VQ100I, XC2C128-7TQG144I | P1-P3

DS093 (v3.2) March 8, 2007 www.xilinx.com 1

Product Specification

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

Features

• Optimized for 1.8V systems

- As fast as 5.7 ns pin-to-pin delays

- As low as 13 μA quiescent current

• Industry’s best 0.18 micron CMOS CPLD

- Optimized architecture for effective logic synthesis

- Multi-voltage I/O operation — 1.5V to 3.3V

• Available in multiple package options

- 100-pin VQFP with 80 user I/O

- 144-pin TQFP with 100 user I/O

- 132-ball CP (0.5mm) BGA with 100 user I/O

- Pb-free available for all packages

• Advanced system features

- Fastest in system programming

· 1.8V ISP using IEEE 1532 (JTAG) interface

- IEEE1149.1 JTAG Boundary Scan Test

- Optional Schmitt-trigger input (per pin)

- Unsurpassed low power management

· DataGATE enable (DGE) signal control

- Two separate I/O banks

- RealDigital 100% CMOS product term generation

- Flexible clocking modes

· Optional DualEDGE triggered registers

· Clock divider (divide by 2,4,6,8,10,12,14,16)

· CoolCLOCK

- Global signal options with macrocell control

· Multiple global clocks with phase selection per

macrocell

· Multiple global output enables

· Global set/reset

- Advanced design security

- Open-drain output option for Wired-OR and LED

drive

- PLA architecture

· Superior pinout retention

· 100% product term routability across function

block

- Optional bus-hold, 3-state or weak pull-up on

selected I/O pins

- Optional configurable grounds on unused I/Os

- Mixed I/O voltages compatible with 1.5V, 1.8V,

2.5V, and 3.3V logic levels

· SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility

- Hot pluggable

Refer to the CoolRunner™-II family data sheet for architec-

ture description.

Description

The CoolRunner-II 128-macrocell device is designed for

both high performance and low power applications. This

lends power savings to high-end communication equipment

and high speed to battery operated devices. Due to the low

power stand-by and dynamic operation, overall system reli-

ability is improved

This device consists of eight Function Blocks inter-con-

nected by a low power Advanced Interconnect Matrix (AIM).

The AIM feeds 40 true and complement inputs to each

Function Block. The Function Blocks consist of a 40 by 56

P-term PLA and 16 macrocells which contain numerous

configuration bits that allow for combinational or registered

modes of operation.

Additionally, these registers can be globally reset or preset

and configured as a D or T flip-flop or as a D latch. There

are also multiple clock signals, both global and local product

term types, configured on a per macrocell basis. Output pin

configurations include slew rate limit, bus hold, pull-up,

open drain and programmable grounds. A Schmitt-trigger

input is available on a per input pin basis. In addition to stor-

ing macrocell output states, the macrocell registers may be

configured as direct input registers to store signals directly

from input pins.

Clocking is available on a global or Function Block basis.

Three global clocks are available for all Function Blocks as

a synchronous clock source. Macrocell registers can be

individually configured to power up to the zero or one state.

A global set/reset control line is also available to asynchro-

nously set or reset selected registers during operation.

Additional local clock, synchronous clock-enable, asynchro-

nous set/reset and output enable signals can be formed

using product terms on a per-macrocell or per-Function

Block basis.

A DualEDGE flip-flop feature is also available on a per mac-

rocell basis. This feature allows high performance synchro-

nous operation based on lower frequency clocking to help

reduce the total power consumption of the device.

Circuitry has also been included to divide one externally

supplied global clock (GCK2) by eight different selections.

This yields divide by even and odd clock frequencies.

The use of the clock divide (division by 2) and DualEDGE

flip-flop gives the resultant CoolCLOCK feature.

DataGATE is a method to selectively disable inputs of the

CPLD that are not of interest during certain points in time.

XC2C128 CoolRunner-II CPLD

DS093 (v3.2) March 8, 2007

Product Specification

XC2C128 CoolRunner-II CPLD

2 www.xilinx.com DS093 (v3.2) March 8, 2007

Product Specification

By mapping a signal to the DataGATE function, lower power

can be achieved due to reduction in signal switching.

Another feature that eases voltage translation is I/O bank-

ing. Two I/O banks are available on the CoolRunner-II 128

macrocell device that permit easy interfacing to 3.3V, 2.5V,

1.8V, and 1.5V devices.

The CoolRunner-II 128 macrocell CPLD is I/O compatible

with various JEDEC I/O standards (see Table 1). This

device is also 1.5V I/O compatible with the use of

Schmitt-trigger inputs.

RealDigital Design Technology

Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron

process technology which is derived from leading edge

FPGA product development. CoolRunner-II CPLDs employ

RealDigital technology, a design technique that makes use

of CMOS technology in both the fabrication and design

methodology. RealDigital technology employs a cascade of

CMOS gates to implement sum of products instead of tradi-

tional sense amplifier methodology. Due to this technology,

Xilinx CoolRunner-II CPLDs achieve both high-perfor-

mance and low power operation.

Supported I/O Standards

The CoolRunner-II 128 macrocell features LVCMOS,

LVTTL, SSTL and HSTL I/O implementations. See Table 1

for I/O standard voltages. The LVTTL I/O standard is a gen-

eral purpose EIA/JEDEC standard for 3.3V applications that

use an LVTTL input buffer and Push-Pull output buffer. The

LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications.

Both HSTL and SSTL make use of a V

REF

pin for JEDEC

compliance. CoolRunner-II CPLDs are also 1.5V I/O com-

patible with the use of Schmitt-trigger inputs.

Table 1: I/O Standards for XC2C128

(1)

IOSTANDARD

Attribute

Output

CCIO

Input

CCIO

Input

REF

Board

Termination

Voltage V

LVTTL 3.3 3.3 N/A N/A

LVCMOS33 3.3 3.3 N/A N/A

LVCMOS25 2.5 2.5 N/A N/A

LVCMOS18 1.8 1.8 N/A N/A

LVCMOS15

(2)

1.5 1.5 N/A N/A

HSTL_1 1.5 1.5 0.75 0.75

SSTL2_1 2.5 2.5 1.25 1.25

SSTL3_1 3.3 3.3 1.5 1.5

(1) For information on assigning Vref pins, see XAPP399

(2) LVCMOS15 requires use of Schmitt-trigger inputs.

Figure 1: I

vs Frequency

Table 2: I

vs Frequency (LVCMOS 1.8V T

= 25°C)

(1)

Frequency (MHz)

0 25 50 75 100 150 175 200 225 250

Typical I

(mA) 0.019 3.97 7.95 11.92 15.89 23.83 27.80 31.93 35.73 39.70

Notes:

1. 16-bit up/down, Resetable binary counter (one counter per function block).

Frequency (MHz)

DS093_041905

(mA)

25020015010050

XC2C128 CoolRunner-II CPLD

DS093 (v3.2) March 8, 2007 www.xilinx.com 3

Product Specification

Recommended Operating Conditions

DC Electrical Characteristics

(Over Recommended Operating Conditions)

Absolute Maximum Ratings

Symbol Description Value Units

Supply voltage relative to ground –0.5 to 2.0 V

CCIO

Supply voltage for output drivers –0.5 to 4.0 V

JTAG

(2)

JTAG input voltage limits –0.5 to 4.0 V

CCAUX

JTAG input supply voltage –0.5 to 4.0 V

(1)

Input voltage relative to ground –0.5 to 4.0 V

(1)

Voltage applied to 3-state output –0.5 to 4.0 V

STG

(3)

Storage Temperature (ambient) –65 to +150 °C

Junction Temperature + 150 °C

Notes:

1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions,

the device pins may undershoot to –2.0V or overshoot to +4.5V, provided this over or undershoot lasts less than 10 ns and with the

forcing current being limited to 200 mA.

2. Valid over commercial temperature range.

3. For soldering guidelines and thermal considerations, see the Device Packaging

information on the Xilinx website. For Pb-free

packages, see XAPP427.

Symbol Parameter Min Max Units

Supply voltage for internal logic

and input buffers

Commercial T

= 0°C to +70°C 1.7 1.9 V

Industrial T

= –40°C to +85°C 1.7 1.9 V

CCIO

Supply voltage for output drivers @ 3.3V operation 3.0 3.6 V

Supply voltage for output drivers @ 2.5V operation 2.3 2.7 V

Supply voltage for output drivers @ 1.8V operation 1.7 1.9 V

Supply voltage for output drivers @ 1.5V operation 1.4 1.6 V

CCAUX

Supply voltage for JTAG programming 1.7 3.6 V

Symbol Parameter Test Conditions Typical Max. Units

CCSB

Standby current Commercial V

= 1.9V, V

CCIO

= 3.6V 30 120 μA

CCSB

Standby current Industrial V

= 1.9V, V

CCIO

= 3.6V 60 200 μA

(1)

Dynamic current f = 1 MHz - 500 μA

f = 50 MHz - 10 mA

JTAG

JTAG input capacitance f = 1 MHz - 10 pF

CLK

Global clock input capacitance f = 1 MHz - 12 pF

I/O capacitance f = 1 MHz - 10 pF

(2)

Input leakage current V

= 0V or V

CCIO

to 3.9V - +/–1 μA

(2)

I/O High-Z leakage V

= 0V or V

CCIO

to 3.9V - +/–1 μA

Notes:

1. 16-bit up/down, Resetable binary counter (one counter per function block).

2. See Quality and Reliability section in CoolRunner-II family data sheet for details.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

XC2C128-7CPG132C

Mfr. #:

Buy XC2C128-7CPG132C

Manufacturer:

Xilinx

Description:

CPLD - Complex Programmable Logic Devices XC2C128-7CPG132C

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

XC2C128-7CPG132C

XC2C128-7CPG132C

Products related to this Datasheet