XC2C128 CoolRunner-II CPLD
18 www.xilinx.com DS093 (v3.2) March 8, 2007
Product Specification
R
Additional Information
Additional information is available for the following CoolRunner-II topics:
• XAPP784: Bulletproof CPLD Design Practices
• XAPP375: Timing Model
• XAPP376: Logic Engine
• XAPP378: Advanced Features
• XAPP382: I/O Characteristics
• XAPP389: Powering CoolRunner-II
• XAPP399: Assigning VREF Pins
To access these and all application notes with their associ-
ated reference designs, click the following link and scroll
down the page until you find the document you want:
CoolRunner-II Data Sheets and Application Notes
Device Packages
Revision History
The following table shows the revision history for this document.
Date Version Revision
10/01/02 1.0 Initial Xilinx release.
5/19/03 2.0 Added bin 6, 7 characterization data.
8/25/03 2.1 Edit Package diagram, other minor formatting edits.
01/26/04 2.2 Update links.
03/01/04 2.3 Fixed cropping on Figure 6.
7/30/04 2.4 Added Pb-free documentation.
10/01/04 2.5 Add Asynchronous Preset/Reset Pulse Width specification to AC Electrical Characteristics.
01/30/05 2.6 Change to I
CCSB
MAX for Commercial and Industrial.
03/07/05 2.7 Delete -4 speed grade. Modifications to Table 1, IOSTANDARDs.
04/21/05 2.8 Recharacterization of AC Specifications
06/28/05 2.9 Move to Product Specification.
03/20/06 3.0 Add Warranty Disclaimer. Add note to Pin Descriptions that
GCK, GSR, and GTS pins can also
be used for general purpose I/O. Replaced Figure 3 with a higher resolution graphic.
02/15/07 3.1 Corrections to timing parameters t
F
, t
CT
, t
DIN
, t
GTS
, t
OEM
and f
TOGGLE
for -6 speed grade.
Corrections to t
DIN
, t
GCK
, t
EN
, t
SUI
, t
ECSU
, t
F
, t
OEM
, F
EXT1
, and F
EXT2
for the -7 speed grade.
Values now match the software. There were no changes to silicon or characterization.
Change to V
IH
specification for 2.5V and 1.8V LVCMOS.
03/08/07 3.2 Fixed typo in note for V
IL
for LVCMOS18; removed note for V
IL
for LVCMOS33.