5CGXFC7C6U19C7N Datasheet 5CEBA4U15I7N, 5CEFA9F23I7N, 5CGXFC9D6F27I7N | P19-P21

Figure 8. ALM for Cyclone V Devices

FPGA Device

Adaptive

LUT

Full

Adder

Reg

Full

Adder

Reg

You can configure up to 25% of the ALMs in the Cyclone V devices as distributed

memory using MLABs.

Related Information

Embedded Memory Capacity in Cyclone V Devices on page 21

Lists the embedded memory capacity for each device.

Variable-Precision DSP Block

Cyclone V devices feature a variable-precision DSP block that supports these features:

• Configurable to support signal processing precisions ranging from 9 x 9, 18 x 18

and 27 x 27 bits natively

• A 64-bit accumulator

• A hard preadder that is available in both 18- and 27-bit modes

• Cascaded output adders for efficient systolic finite impulse response (FIR) filters

• Internal coefficient register banks, 8 deep, for each multiplier in 18- or 27-bit

mode

• Fully independent multiplier operation

• A second accumulator feedback register to accommodate complex multiply-

accumulate functions

• Fully independent Efficient support for single-precision floating point arithmetic

• The inferability of all modes by the Intel Quartus Prime design software

Cyclone V Device Overview

CV-51001 | 2018.05.07

Cyclone V Device Overview

Table 16. Variable-Precision DSP Block Configurations for Cyclone V Devices

Usage Example Multiplier Size (Bit) DSP Block Resource

Low precision fixed point for video

applications

Three 9 x 9 1

Medium precision fixed point in FIR

filters

Two 18 x 18 1

FIR filters and general DSP usage Two 18 x 18 with accumulate 1

High precision fixed- or floating-point

implementations

One 27 x 27 with accumulate 1

You can configure each DSP block during compilation as independent three 9 x 9, two

18 x 18, or one 27 x 27 multipliers. With a dedicated 64 bit cascade bus, you can

cascade multiple variable-precision DSP blocks to implement even higher precision

DSP functions efficiently.

Table 17. Number of Multipliers in Cyclone V Devices

The table lists the variable-precision DSP resources by bit precision for each Cyclone V device.

Variant Member

Code

Variable-

precision

DSP Block

Independent Input and Output

Multiplications Operator

18 x 18

Multiplier

Adder Mode

18 x 18

Multiplier

Adder

Summed

with 36 bit

Input

9 x 9

Multiplier

18 x 18

Multiplier

27 x 27

Multiplier

Cyclone V E A2 25 75 50 25 25 25

A4 66 198 132 66 66 66

A5 150 450 300 150 150 150

A7 156 468 312 156 156 156

A9 342 1,026 684 342 342 342

Cyclone V

C3 57 171 114 57 57 57

C4 70 210 140 70 70 70

C5 150 450 300 150 150 150

C7 156 468 312 156 156 156

C9 342 1,026 684 342 342 342

Cyclone V GT D5 150 450 300 150 150 150

D7 156 468 312 156 156 156

D9 342 1,026 684 342 342 342

Cyclone V SE A2 36 108 72 36 36 36

A4 84 252 168 84 84 84

A5 87 261 174 87 87 87

A6 112 336 224 112 112 112

Cyclone V SX C2 36 108 72 36 36 36

C4 84 252 168 84 84 84

C5 87 261 174 87 87 87

continued...

Cyclone V Device Overview

CV-51001 | 2018.05.07

Cyclone V Device Overview

Variant Member

Code

Variable-

precision

DSP Block

Independent Input and Output

Multiplications Operator

18 x 18

Multiplier

Adder Mode

18 x 18

Multiplier

Adder

Summed

with 36 bit

Input

9 x 9

Multiplier

18 x 18

Multiplier

27 x 27

Multiplier

C6 112 336 224 112 112 112

Cyclone V ST D5 87 261 174 87 87 87

D6 112 336 224 112 112 112

Embedded Memory Blocks

The embedded memory blocks in the devices are flexible and designed to provide an

optimal amount of small- and large-sized memory arrays to fit your design

requirements.

Types of Embedded Memory

The Cyclone V devices contain two types of memory blocks:

• 10 Kb M10K blocks—blocks of dedicated memory resources. The M10K blocks are

ideal for larger memory arrays while still providing a large number of independent

ports.

• 640 bit memory logic array blocks (MLABs)—enhanced memory blocks that are

configured from dual-purpose logic array blocks (LABs). The MLABs are ideal for

wide and shallow memory arrays. The MLABs are optimized for implementation of

shift registers for digital signal processing (DSP) applications, wide shallow FIFO

buffers, and filter delay lines. Each MLAB is made up of ten adaptive logic modules

(ALMs). In the Cyclone V devices, you can configure these ALMs as ten 32 x 2

blocks, giving you one 32 x 20 simple dual-port SRAM block per MLAB.

Embedded Memory Capacity in Cyclone V Devices

Table 18. Embedded Memory Capacity and Distribution in Cyclone V Devices

Variant

Member

Code

M10K MLAB

Total RAM Bit

(Kb)Block RAM Bit (Kb) Block RAM Bit (Kb)

Cyclone V E A2 176 1,760 314 196 1,956

A4 308 3,080 485 303 3,383

A5 446 4,460 679 424 4,884

A7 686 6,860 1338 836 7,696

A9 1,220 12,200 2748 1,717 13,917

Cyclone V GX C3 135 1,350 291 182 1,532

C4 250 2,500 678 424 2,924

C5 446 4,460 678 424 4,884

C7 686 6,860 1338 836 7,696

C9 1,220 12,200 2748 1,717 13,917

continued...

Cyclone V Device Overview

CV-51001 | 2018.05.07

Cyclone V Device Overview

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P37

5CGXFC7C6U19C7N

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Manufacturer:

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Description:

FPGA - Field Programmable Gate Array FPGA - Cyclone V GX 5648 LABs 224 IOs

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