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5CGXFC7C6U19C7N

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37
External Memory Performance
Table 20. External Memory Interface Performance in Cyclone V Devices
The maximum and minimum operating frequencies depend on the memory interface standards and the
supported delay-locked loop (DLL) frequency listed in the device datasheet.
Interface Voltage
(V)
Maximum Frequency (MHz) Minimum Frequency
(MHz)
Hard Controller Soft Controller
DDR3 SDRAM 1.5 400 303 303
1.35 400 303 303
DDR2 SDRAM 1.8 400 300 167
LPDDR2 SDRAM 1.2 333 300 167
Related Information
External Memory Interface Spec Estimator
For the latest information and to estimate the external memory system
performance specification, use Intel's External Memory Interface Spec Estimator
tool.
HPS External Memory Performance
Table 21. HPS External Memory Interface Performance
The hard processor system (HPS) is available in Cyclone V SoC devices only.
Interface
Voltage (V) HPS Hard Controller (MHz)
DDR3 SDRAM 1.5 400
1.35 400
DDR2 SDRAM 1.8 400
LPDDR2 SDRAM 1.2 333
Related Information
External Memory Interface Spec Estimator
For the latest information and to estimate the external memory system
performance specification, use Intel's External Memory Interface Spec Estimator
tool.
Low-Power Serial Transceivers
Cyclone V devices deliver the industry’s lowest power 6.144 Gbps transceivers at an
estimated 88 mW maximum power consumption per channel. Cyclone V transceivers
are designed to be compliant with a wide range of protocols and data rates.
Transceiver Channels
The transceivers are positioned on the left outer edge of the device. The transceiver
channels consist of the physical medium attachment (PMA), physical coding sublayer
(PCS), and clock networks.
Cyclone V Device Overview
CV-51001 | 2018.05.07
Cyclone V Device Overview
25
Figure 10. Device Chip Overview for Cyclone V GX and GT Devices
The figure shows a Cyclone V FPGA with transceivers. Different Cyclone V devices may have a different
floorplans than the one shown here.
I/O, LVDS, and Memory Interface
I/O, LVDS, and Memory Interface
I/O, LVDS, and Memory Interface
Transceiver PMA Blocks
Fractional PLLs
Hard PCS Blocks
Fractional PLL
Fractional PLLs
PCIe Hard IP Blocks
Hard Memory Controller
Hard Memory Controller
Core Logic Fabric and MLABs
Variable-Precision DSP Blocks
M10K Internal Memory Blocks
Transceiver
PMA
Transceiver
PMA
Transceiver
PMA
Hard
PCS
Hard
PCS
Hard
PCS
Clock Networks
Transceiver
Individual Channels
PMA Features
To prevent core and I/O noise from coupling into the transceivers, the PMA block is
isolated from the rest of the chip—ensuring optimal signal integrity. For the
transceivers, you can use the channel PLL of an unused receiver PMA as an additional
transmit PLL.
Table 22. PMA Features of the Transceivers in Cyclone V Devices
Features Capability
Backplane support Driving capability up to 6.144 Gbps
PLL-based clock recovery Superior jitter tolerance
Programmable deserialization and word
alignment
Flexible deserialization width and configurable word alignment pattern
Equalization and pre-emphasis • Up to 14.37 dB of pre-emphasis and up to 4.7 dB of equalization
• No decision feedback equalizer (DFE)
Ring oscillator transmit PLLs 614 Mbps to 6.144 Gbps
Input reference clock range 20 MHz to 400 MHz
Transceiver dynamic reconfiguration Allows the reconfiguration of a single channel without affecting the operation of
other channels
Cyclone V Device Overview
CV-51001 | 2018.05.07
Cyclone V Device Overview
26
PCS Features
The Cyclone V core logic connects to the PCS through an 8, 10, 16, 20, 32, or 40 bit
interface, depending on the transceiver data rate and protocol. Cyclone V devices
contain PCS hard IP to support PCIe Gen1 and Gen2, Gbps Ethernet (GbE), Serial
RapidIO
®
(SRIO), and Common Public Radio Interface (CPRI).
Most of the standard and proprietary protocols from 614 Mbps to 6.144 Gbps are
supported.
Table 23. Transceiver PCS Features for Cyclone V Devices
PCS Support Data Rates
(Gbps)
Transmitter Data Path Feature Receiver Data Path Feature
3-Gbps and 6-Gbps Basic 0.614 to 6.144 • Phase compensation FIFO
• Byte serializer
• 8B/10B encoder
• Transmitter bit-slip
• Word aligner
• Deskew FIFO
• Rate-match FIFO
• 8B/10B decoder
• Byte deserializer
• Byte ordering
• Receiver phase compensation
FIFO
PCIe Gen1
(x1, x2, x4)
2.5 and 5.0 • Dedicated PCIe PHY IP core
• PIPE 2.0 interface to the core
logic
• Dedicated PCIe PHY IP core
• PIPE 2.0 interface to the core
logic
PCIe Gen2
( x1, x2, x4)
(12)
GbE 1.25 • Custom PHY IP core with preset
feature
• GbE transmitter synchronization
state machine
• Custom PHY IP core with preset
feature
• GbE receiver synchronization
state machine
XAUI
(13)
3.125 • Dedicated XAUI PHY IP core
• XAUI synchronization state
machine for bonding four
channels
• Dedicated XAUI PHY IP core
• XAUI synchronization state
machine for realigning four
channels
HiGig 3.75
SRIO 1.3 and 2.1 1.25 to 3.125 • Custom PHY IP core with preset
feature
• SRIO version 2.1-compliant x2
and x4 channel bonding
• Custom PHY IP core with preset
feature
• SRIO version 2.1-compliant x2
and x4 deskew state machine
SDI, SD/HD, and 3G-SDI 0.27
(14)
, 1.485,
and 2.97
Custom PHY IP core with preset
feature
Custom PHY IP core with preset
feature
JESD204A 0.3125
(15)
to
3.125
continued...
(12)
PCIe Gen2 is supported for Cyclone V GT and ST devices. The PCIe Gen2 x4 support is
PCIe-compatible.
(13)
XAUI is supported through the soft PCS.
(14)
The 0.27-Gbps data rate is supported using oversampling user logic that you must implement
in the FPGA fabric.
(15)
The 0.3125-Gbps data rate is supported using oversampling user logic that you must
implement in the FPGA fabric.
Cyclone V Device Overview
CV-51001 | 2018.05.07
Cyclone V Device Overview
27
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37

5CGXFC7C6U19C7N

Mfr. #:
Buy 5CGXFC7C6U19C7N
Manufacturer:
Intel / Altera
Description:
FPGA - Field Programmable Gate Array FPGA - Cyclone V GX 5648 LABs 224 IOs
Lifecycle:
New from this manufacturer.
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