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5CGXFC7C6U19C7N

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37
Note: Although the FPGA fabric and HPS are on separate power domains, the HPS must
remain powered up during operation while the FPGA fabric can be powered up or down
as required.
Related Information
Cyclone V Device Family Pin Connection Guidelines
Provides detailed information about power supply pin connection guidelines and
power regulator sharing.
Hardware and Software Development
For hardware development, you can configure the HPS and connect your soft logic in
the FPGA fabric to the HPS interfaces using the Platform Designer (Standard) system
integration tool in the Intel Quartus Prime software.
For software development, the Arm-based SoC devices inherit the rich software
development ecosystem available for the Arm Cortex-A9 MPCore processor. The
software development process for Intel SoCs follows the same steps as those for other
SoC devices from other manufacturers. Support for Linux, VxWorks
®
, and other
operating systems is available for the SoCs. For more information on the operating
systems support availability, contact the Intel sales team.
You can begin device-specific firmware and software development on the Intel SoC
Virtual Target. The Virtual Target is a fast PC-based functional simulation of a target
development system—a model of a complete development board that runs on a PC.
The Virtual Target enables the development of device-specific production software that
can run unmodified on actual hardware.
Related Information
International Altera Sales Support Offices
Dynamic and Partial Reconfiguration
The Cyclone V devices support dynamic reconfiguration and partial reconfiguration.
Dynamic Reconfiguration
The dynamic reconfiguration feature allows you to dynamically change the transceiver
data rates, PMA settings, or protocols of a channel, without affecting data transfer on
adjacent channels. This feature is ideal for applications that require on-the-fly
multiprotocol or multirate support. You can reconfigure the PMA and PCS blocks with
dynamic reconfiguration.
Partial Reconfiguration
Note: The partial reconfiguration feature is available for Cyclone V E, GX, SE, and SX devices
with the "SC" suffix in the part number. For device availability and ordering, contact
your local Intel sales representatives.
Partial reconfiguration allows you to reconfigure part of the device while other sections
of the device remain operational. This capability is important in systems with critical
uptime requirements because it allows you to make updates or adjust functionality
without disrupting services.
Cyclone V Device Overview
CV-51001 | 2018.05.07
Cyclone V Device Overview
31
Apart from lowering cost and power consumption, partial reconfiguration increases the
effective logic density of the device because placing device functions that do not
operate simultaneously is not necessary. Instead, you can store these functions in
external memory and load them whenever the functions are required. This capability
reduces the size of the device because it allows multiple applications on a single
device—saving the board space and reducing the power consumption.
Intel simplifies the time-intensive task of partial reconfiguration by building this
capability on top of the proven incremental compile and design flow in the Intel
Quartus Prime design software. With the Intel solution, you do not need to know all
the intricate device architecture details to perform a partial reconfiguration.
Partial reconfiguration is supported through the FPP x16 configuration interface. You
can seamlessly use partial reconfiguration in tandem with dynamic reconfiguration to
enable simultaneous partial reconfiguration of both the device core and transceivers.
Enhanced Configuration and Configuration via Protocol
Cyclone V devices support 1.8 V, 2.5 V, 3.0 V, and 3.3 V programming voltages and
several configuration schemes.
Table 24. Configuration Schemes and Features Supported by Cyclone V Devices
Mode Data
Width
Max Clock
Rate
(MHz)
Max Data
Rate
(Mbps)
Decompressi
on
Design
Security
Partial
Reconfigurat
ion
(18)
Remote
System
Update
AS through the EPCS
and EPCQ serial
configuration device
1 bit, 4
bits
100 — Yes Yes — Yes
PS through CPLD or
external
microcontroller
1 bit 125 125 Yes Yes — —
FPP 8 bits 125 — Yes Yes — Parallel flash
loader
16 bits 125 — Yes Yes Yes
CvP (PCIe) x1, x2,
and x4
lanes
— — Yes Yes Yes —
JTAG 1 bit 33 33 — — — —
Instead of using an external flash or ROM, you can configure the Cyclone V devices
through PCIe using CvP. The CvP mode offers the fastest configuration rate and
flexibility with the easy-to-use PCIe hard IP block interface. The Cyclone V CvP
implementation conforms to the PCIe 100 ms power-up-to-active time requirement.
Related Information
Configuration via Protocol (CvP) Implementation in Intel FPGAs User Guide
Provides more information about CvP.
(18)
The partial reconfiguration feature is available for Cyclone V E, GX, SE, and SX devices with
the "SC" suffix in the part number. For device availability and ordering, contact your local Intel
sales representatives.
Cyclone V Device Overview
CV-51001 | 2018.05.07
Cyclone V Device Overview
32
Power Management
Leveraging the FPGA architectural features, process technology advancements, and
transceivers that are designed for power efficiency, the Cyclone V devices consume
less power than previous generation Cyclone FPGAs:
• Total device core power consumption—less by up to 40%.
• Transceiver channel power consumption—less by up to 50%.
Additionally, Cyclone V devices contain several hard IP blocks that reduce logic
resources and deliver substantial power savings of up to 25% less power than
equivalent soft implementations.
Document Revision History for Cyclone V Device Overview
Document
Version
Changes
2018.05.07 • Added the low power option ("L" suffix) for Cyclone V SE and Cyclone V SX devices in the Sample
Ordering Code and Available Options diagrams.
• Rebranded as Intel.
Date Version Changes
December 2017 2017.12.18 • Updated ALM resources for Cyclone V E, Cyclone V SE, Cyclone V SX, and
Cyclone V ST devices.
June 2016 2016.06.10 Updated Cyclone V GT speed grade to –7 in Sample Ordering Code and
Available Options for Cyclone V GT Devices diagram.
December 2015 2015.12.21 • Added descriptions to package plan tables for Cyclone V GT and ST
devices.
• Changed instances of Quartus II to Quartus Prime.
June 2015 2015.06.12 • Replaced a note to partial reconfiguration feature. Note: The partial
reconfiguration feature is available for Cyclone V E, GX, SE, and SX
devices with the "SC" suffix in the part number. For device availability and
ordering, contact your local Altera sales representatives.
• Updated logic elements (LE) (K) for the following devices:
— Cyclone V E A7: Updated from 149.5 to 150
— Cyclone V GX C3: Updated from 35.5 to 36
— Cyclone V GX C7: Updated from 149.7 to 150
— Cyclone V GT D7: Updated from 149.5 to 150
• Updated MLAB (Kb) in Maximum Resource Counts for Cyclone V GX
Devices table as follows:
— Cyclone V GX C3: Updated from 291 to 182
— Cyclone V GX C4: Updated from 678 to 424
— Cyclone V GX C5: Updated from 678 to 424
— Cyclone V GX C7: Updated from 1,338 to 836
— Cyclone V GX C9: Updated from 2,748 to 1,717
continued...
Cyclone V Device Overview
CV-51001 | 2018.05.07
Cyclone V Device Overview
33
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5CGXFC7C6U19C7N

Mfr. #:
Buy 5CGXFC7C6U19C7N
Manufacturer:
Intel / Altera
Description:
FPGA - Field Programmable Gate Array FPGA - Cyclone V GX 5648 LABs 224 IOs
Lifecycle:
New from this manufacturer.
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