 87321I Data Sheet
©2016 Integrated Device Technology, Inc Revision A January 25, 201613
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V
CC
– 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
– 0.9V
(V
CC_MAX
V
OH_MAX
)
= 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
– 1.7V
(V
CC_MAX
V
OL_MAX
)
= 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CC_MAX
– 2V))/R
L
] * (V
CC_MAX
– V
OH_MAX
) = [(2V – (V
CC
_MAX
V
OH_MAX
))
/R
L
] * (V
CC_MAX
– V
OH_MAX
) =
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
– V
OL_MAX
) = [(2V – (V
CC
_MAX
V
OL_MAX
))
/R
L
] * (V
CC_MAX
– V
OL_MAX
) =
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION 87321I Data Sheet
©2016 Integrated Device Technology, Inc Revision A January 25, 201614
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for 87321I is: 309
TABLE 7. θ
JA
VS. AIR FLOW TABLE FOR 8 LEAD SOIC
θ
JA
by Velocity (Linear Feet per Minute)
0 200 500
Multi-Layer PCB, JEDEC Standard Test Boards 95.0°C/W 88.4°C/W 83.7°C/W 87321I Data Sheet
©2016 Integrated Device Technology, Inc Revision A January 25, 201615
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
TABLE 8. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MS-012
SYMBOL
Millimeters
MINIMUN MAXIMUM
N8
A 1.35 1.75
A1 0.10 0.25
B 0.33 0.51
C 0.19 0.25
D 4.80 5.00
E 3.80 4.00
e 1.27 BASIC
H 5.80 6.20
h 0.25 0.50
L 0.40 1.27
α

#### 87321AMILFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products 1 LVPECL OUT DIVIDER
Lifecycle:
New from this manufacturer.
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