1. General description
The GTL2014 is a 4-bit translating transceiver designed for 3.3 V LVTTL system interface
with a GTL−/GTL/GTL+ bus, where GTL−/GTL/GTL+ refers to the reference voltage of the
GTL bus and the input/output voltage thresholds associated with it.
The direction pin allows the part to function as either a GTL to LVTTL sampling receiver or
as a LVTTL to GTL interface.
The GTL2014 LVTTL inputs (only) are tolerant up to 5.5 V allowing direct access to TTL or
5 V CMOS inputs. The LVTTL outputs are not 5.5 V tolerant.
The GTL2014 GTL inputs and outputs operate up to 3.6 V, allowing the device to be used
in higher voltage open-drain output applications.
GTL2014 is pin-to-pin backward compatible to the GTL2005 (labels for A port and B port
are interchanged). GTL2014’s V
tracks down to 0.5 V for low voltage CPU, propagation
delays are slightly longer, while GTL2005’s V
linearity degrades below 0.8 V and has
shorter propagation delay.
2. Features and benefits
Operates as a 4-bit GTL−/GTL/GTL+ sampling receiver or as a LVTTL to
3.0 V to 3.6 V operation with 5 V tolerant LVTTL input
GTL input and output 3.6 V tolerant
adjustable from 0.5 V to V
Partial power-down permitted
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
4-bit LVTTL to GTL transceiver
Rev. 3 — 14 June 2012 Product data sheet
Fig 1. GTL2005/GTL2014 positioning