74LVC_LVCH1T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 6 August 2012 23 of 33
NXP Semiconductors
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
14.2 Bidirectional logic level-shifting application
Figure 16 shows the 74LVC1T45; 74LVCH1T45 being used in a bidirectional logic
level-shifting application. Since the device does not have an output enable pin, the system
designer should take precautions to avoid bus contention between system-1 and
system-2 when changing directions.
Table 17 provides a sequence that illustrates data transmission from system-1 to
system-2 and then from system-2 to system-1.
[1] H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
Pull-up or pull-down only needed for 74LVC1T45.
Fig 16. Bidirectional logic level-shifting application
Table 17. Description bidirectional logic level-shifting application
[1]
State DIR CTRL I/O-1 I/O-2 Description
1 H output input system-1 data to system-2
2 H Z Z system-2 is getting ready to send data to system-1.
I/O-1 and I/O-2 are disabled. The bus-line state
depends on bus hold.
3 L Z Z DIR bit is set LOW. I/O-1 and I/O-2 are still disabled.
The bus-line state depends on bus hold.
4 L input output system-2 data to system-1
001aaj995
74LVC1T45
74LVCH1T45
V
CC1
V
CC1
V
CC2
V
CC2
1
2
3
V
CC(A)
GND
system-1 system-2
A
6
5
4
V
CC(B)
DIR
B
I/O-1 I/O-2
PULL-UP/DOWN
DIR CTRL
PULL-UP/DOWN
