ADVANCED CORES
The T4 family of processors are based
on the new Power Architecture
®
e6500
core. The e6500 uses a 64-bit seven-
stage pipeline for low latency response
to unpredictable code execution paths,
boosting single-threaded performance.
The e6500 also offers higher aggregate
instructions per clock at lower power with
an innovative “fused core” approach
to threading. The e6500 core’s fully
resourced dual threads provide 1.7 times
the performance of a single thread.
The e6500 cores are clustered in banks
of four cores sharing a 2 MB L2 cache,
allowing efficient sharing of code and data
within a multicore cluster. Each e6500
core implements the AltiVec
®
technology
SIMD engine, dramatically boosting the
performance of heavy math algorithms
with DSP-like performance. The e6500
core features include:
} Up to 1.8 GHz dual-threaded operation
} 7 DMIPS/MHz per core
} Advanced power saving modes,
including state retention power gating
VIRTUALIZATION
The T4 family of processors includes
support for hardware-assisted
virtualization. The e6500 core offers an
extra core privilege level (hypervisor)
and hardware offload of logical to
real address translation. In addition,
the T4 family of processors includes
platform-level enhancements supporting
I/O virtualization with DMA memory
protection through IOMMUs and
configurable “storage profiles” that
provide isolation of I/O buffers between
guest environments. Virtualization
software for the T4 family includes kernel
virtualization machine (KVM), Linux
®
containers, hypervisor and commercial
virtualization software from Enea
®
,
Green Hills Software
®
, Mentor Graphics
®
and Wind River.
CoreNet Coherency Fabric
Real-Time Debug
Security
5.0
Pattern
Match
Engine
2.0
RMAN
DCE
1.0
Queue
Mgr.
Buffer
Mgr.
Peripheral Access
Management Unit
PAMU
PAM U PAMU PAMU
16-Lane 10 GHz SerDes 16-Lane 10 GHz SerDes
64-bit DDR3/3 L
Memory Controller
64-bit DDR3/3 L
Memory Controller
64-bit DDR3/3 L
Memory Controller
512 KB CoreNet
®
Platform Cache
512 KB CoreNet
Platform Cache
512 KB CoreNet
Platform Cache
Parse, Classify,
Distribute
Frame Manager
1GE
1GE
HiGig DCB
1GE
1GE
1GE
1/
10G
1/
10G
1GE
Parse, Classify,
Distribute
Frame Manager
1GE
1GE
HiGig DCB
1GE
1GE
1GE
1/
10G
1/
10G
1GE
2 x USB 2.0 w/PHY
Security Monitor
Security Fuse Processor
IFC
Power Management
SD/MMC
4 x DUART
4 x I
2
C
SPI, GPIO
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
2 MB Banked L2
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
Core Complex (CPU, L2, L3 Cache) Basic Peripherals and Interconnect Accelerators and Memory Control Networking Elements
SRIO
SRIO
PCIe
PCIe
PCIe
®
PCIe
Watchpoint
Cross
Trigger
Perf.
Monitor
Trace
Aurora
SATA 2.0
SATA 2.0
Interlaken LA-1
3 x
DMA
RapidI O
Message
Unit
T1 T2
Power
Architecture
®
e6500
T1 T2
Power
Architecture
e6500
T1 T2
Power
Architecture
e6500
T1 T2
Power
Architecture
e6500
QORIQ T4240 PROCESSOR BLOCK DIAGRAM
QorIQ T4240 PROCESSOR BLOCK DIAGRAM
DPAA HARDWARE ACCELERATORS
Frame Manager (FMAN) 50 Gbit/s classify, parse and distribute
Buffer Manager (BMAN) 64 buffer pools
Queue Manager (QMAN) Up to 2
24
queues
RapidIO Manager (RMAN) Seamless mapping to DPAA
Security (SEC) 40 Gbit/s: 3 DES, AES; 20 Gbit/s: Kasumi/F8
Pattern Matching Engine (PME) 10 Gbit/s
Data Compression Engine (DCE) 20 Gbit/s aggregate
DATA PATH ACCELERATION
ARCHITECTURE (DPAA)
The T4 family of processors enhances
the QorIQ DPAA, an innovative
multicore infrastructure for scheduling
work to cores (physical and virtual),
hardware accelerators and network
interfaces. The FMAN, a primary
element of the DPAA, parses
headers from incoming packets and
classifies and selects data buffers
with optional policing and congestion
management. The FMAN passes its
work to the QMAN, which assigns
it to cores or accelerators with a
multilevel scheduling hierarchy. The
T4240 processor’s implementation
of the DPAA offers accelerators for
cryptography, enhanced regular
expression pattern matching and
compression/decompression.
SYSTEM PERIPHERALS AND
NETWORKING
For networking, there are dual FMANs
with an aggregate of up to 16 any-speed
MAC controllers that connect to PHYs,
switches and backplanes over RGMII,
SGMII, QSGMII, HiGig2, XAUI, XFI and
10Gbase-KR. The FMAN also supports
new quality-of-service features through
egress traffic shaping and priority
flow control for data center bridging
in converged data center networking
applications. High-speed system
expansion is supported through four PCI
Express controllers that support varieties
of lane lengths for PCIe specification
3.0, including endpoint SR-IOV with
128 virtual functions. Other peripheral
interfaces include SRIO, Interlaken-LA,
SATA, SD/MMC, I
2
C, UART, SPI, a NOR/
NAND controller, GPIO and a 1866 MT/s
DDR3L controller.
