XC5VLX85T-1FFG1136I

Virtex-5 Family Overview
4 www.xilinx.com DS100 (v5.0) February 6, 2009
Product Specification
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Digitally Controlled Impedance (DCI)
Active I/O Termination
Optional series or parallel termination
Temperature and voltage compensation
Makes board layout much easier
Reduces resistors
Places termination in the ideal location, at the signal
source or destination
Configuration
Support for platform Flash, standard SPI Flash, or
standard parallel NOR Flash configuration
Bitstream support with dedicated fallback
reconfiguration logic
256-bit AES bitstream decryption provides intellectual
property security and prevents design copying
Improved bitstream error detection/correction capability
Auto bus width detection capability
Partial Reconfiguration via ICAP port
Advanced Flip-Chip Packaging
Pre-engineered packaging technology for proven
superior signal integrity
Minimized inductive loops from signal to return
Optimal signal-to-PWR/GND ratios
Reduces SSO induced noise by up to 7x
Pb-Free and standard packages
System Monitor
On-Chip temperature measurement (±4°C)
On-Chip power supply measurement (±1%)
Easy to use, self-contained
No design required for basic operation
Autonomous monitoring of all on-chip sensors
User programmable alarm thresholds for on-chip
sensors
User accessible 10-bit 200kSPS ADC
Automatic calibration of offset and gain error
DNL = ±0.9 LSBs maximum
Up to 17 external analog input channels supported
0V to 1V input range
Monitor external sensors e.g., voltage, temperature
General purpose analog inputs
Full access from fabric or JTAG TAP to System Monitor
Fully operational prior to FPGA configuration and
during device power down (access via JTAG TAP only)
65-nm Copper CMOS Process
1.0V Core Voltage
12-layer metal provides maximum routing capability
and accommodates hard-IP immersion
Triple-oxide technology for proven reduced static power
consumption
System Blocks Specific to the LXT, SXT, TXT, and FXT Devices
Integrated Endpoint Block for PCI Express
Compliance
Works in conjunction with RocketIO GTP transceivers
(LXT and SXT) and GTX transceivers (TXT and FXT)
to deliver full PCI Express Endpoint functionality with
minimal FPGA logic utilization.
Compliant with the PCI Express Base Specification 1.1
PCI Express Endpoint block or Legacy PCI Express
Endpoint block
x8, x4, or x1 lane width
Power management support
Block RAMs used for buffering
Fully buffered transmit and receive
Management interface to access PCI Express
configuration space and internal configuration
Supports the full range of maximum payload sizes
Up to 6 x 32 bit or 3 x 64 bit BARs (or a combination of
32 bit and 64 bit)
Tri-Mode Ethernet Media Access Controller
Designed to the IEEE 802.3-2002 specification
Operates at 10, 100, and 1,000 Mb/s
Supports tri-mode auto-negotiation
Receive address filter (5 address entries)
Fully monolithic 1000Base-X solution with RocketIO
GTP transceivers
Supports multiple external PHY connections (RGMII,
GMII, etc.) interfaces through soft logic and SelectIO
resources
Supports connection to external PHY device through
SGMII using soft logic and RocketIO GTP transceivers
Receive and transmit statistics available through
separate interface
Separate host and client interfaces
Support for jumbo frames
Support for VLAN
Flexible, user-configurable host interface
Supports IEEE 802.3ah-2004 unidirectional mode
Virtex-5 Family Overview
DS100 (v5.0) February 6, 2009 www.xilinx.com
Product Specification 5
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RocketIO GTP Transceivers (LXT/SXT only)
Full-duplex serial transceiver capable of 100 Mb/s to
3.75 Gb/s baud rates
8B/10B, user-defined FPGA logic, or no encoding
options
Channel bonding support
CRC generation and checking
Programmable pre-emphasis or pre-equalization for
the transmitter
Programmable termination and voltage swing
Programmable equalization for the receiver
Receiver signal detect and loss of signal indicator
User dynamic reconfiguration using secondary
configuration bus
Out of Band (OOB) support for Serial ATA (SATA)
Electrical idle, beaconing, receiver detection, and PCI
Express and SATA spread-spectrum clocking support
Less than 100 mW typical power consumption
Built-in PRBS Generators and Checkers
RocketIO GTX Transceivers (TXT/FXT only)
Full-duplex serial transceiver capable of 150 Mb/s to
6.5 Gb/s baud rates
8B/10B encoding and programmable gearbox to
support 64B/66B and 64B/67B encoding, user-defined
FPGA logic, or no encoding options
Channel bonding support
CRC generation and checking
Programmable pre-emphasis or pre-equalization for
the transmitter
Programmable termination and voltage swing
Programmable continuous time equalization for the
receiver
Programmable decision feedback equalization for the
receiver
Receiver signal detect and loss of signal indicator
User dynamic reconfiguration using secondary
configuration bus
OOB support (SATA)
Electrical idle, beaconing, receiver detection, and
PCI Express spread-spectrum clocking support
Low-power operation at all line rates
PowerPC 440 RISC Cores (FXT only)
Embedded PowerPC 440 (PPC440) cores
Up to 550 MHz operation
Greater than 1000 DMIPS per core
Seven-stage pipeline
Multiple instructions per cycle
Out-of-order execution
32 Kbyte, 64-way set associative level 1 instruction
cache
32 Kbyte, 64-way set associative level 1 data cache
Book E compliant
Integrated crossbar for enhanced system performance
128-bit Processor Local Buses (PLBs)
Integrated scatter/gather DMA controllers
Dedicated interface for connection to DDR2 memory
controller
Auto-synchronization for non-integer PLB-to-CPU clock
ratios
Auxiliary Processor Unit (APU) Interface and Controller
Direct connection from PPC440 embedded block to
FPGA fabric-based coprocessors
128-bit wide pipelined APU Load/Store
Support of autonomous instructions: no pipeline stalls
Programmable decode for custom instructions
Virtex-5 Family Overview
6 www.xilinx.com DS100 (v5.0) February 6, 2009
Product Specification
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Architectural Description
Virtex-5 FPGA Array Overview
Virtex-5 devices are user-programmable gate arrays with various configurable elements and embedded cores optimized for
high-density and high-performance system designs. Virtex-5 devices implement the following functionality:
I/O blocks provide the interface between package pins
and the internal configurable logic. Most popular and
leading-edge I/O standards are supported by
programmable I/O blocks (IOBs). The IOBs can be
connected to very flexible ChipSync logic for enhanced
source-synchronous interfacing. Source-synchronous
optimizations include per-bit deskew (on both input and
output signals), data serializers/deserializers, clock
dividers, and dedicated I/O and local clocking
resources.
Configurable Logic Blocks (CLBs), the basic logic
elements for Xilinx® FPGAs, provide combinatorial and
synchronous logic as well as distributed memory and
SRL32 shift register capability. Virtex-5 FPGA CLBs
are based on real 6-input look-up table technology and
provide superior capabilities and performance
compared to previous generations of programmable
logic.
Block RAM modules provide flexible 36 Kbit true dual-
port RAM that are cascadable to form larger memory
blocks. In addition, Virtex-5 FPGA block RAMs contain
optional programmable FIFO logic for increased device
utilization. Each block RAM can also be configured as
two independent 18 Kbit true dual-port RAM blocks,
providing memory granularity for designs needing
smaller RAM blocks.
Cascadable embedded DSP48E slices with 25 x 18
two’s complement multipliers and 48-bit
adder/subtracter/accumulator provide massively
parallel DSP algorithm support. In addition, each
DSP48E slice can be used to perform bitwise logical
functions.
Clock Management Tile (CMT) blocks provide the most
flexible, highest-performance clocking for FPGAs. Each
CMT contains two Digital Clock Manager (DCM) blocks
(self-calibrating, fully digital), and one PLL block (self-
calibrating, analog) for clock distribution delay
compensation, clock multiplication/division, coarse-
/fine-grained clock phase shifting, and input clock jitter
filtering.
Additionally, LXT, SXT, TXT, and FXT devices also contain:
Integrated Endpoint blocks for PCI Express designs
providing x1, x4, or x8 PCI Express Endpoint
functionality. When used in conjunction with RocketIO
transceivers, a complete PCI Express Endpoint can be
implemented with minimal FPGA logic utilization.
10/100/1000 Mb/s Ethernet media-access control
blocks offer Ethernet capability.
LXT and SXT devices contain:
RocketIO GTP transceivers capable of running up to
3.75 Gb/s. Each GTP transceiver supports full-duplex,
clock-and-data recovery.
TXT and FXT devices contain:
GTX transceivers capable of running up to 6.5 Gb/s.
Each GTX transceiver supports full-duplex, clock-and-
data recovery.
FXT devices contain:
Embedded IBM PowerPC 440 RISC CPUs. Each
PowerPC 440 CPU is capable of running up to
550 MHz. Each PowerPC 440 CPU also has an APU
(Auxiliary Processor Unit) interface that supports
hardware acceleration, and an integrated cross-bar for
high data throughput.
The general routing matrix (GRM) provides an array of
routing switches between each internal component. Each
programmable element is tied to a switch matrix, allowing
multiple connections to the general routing matrix. The
overall programmable interconnection is hierarchical and
designed to support high-speed designs. In Virtex-5
devices, the routing connections are optimized to support
CLB interconnection in the fewest number of “hops.
Reducing hops greatly increases post place-and-route
(PAR) design performance.
All programmable elements, including the routing
resources, are controlled by values stored in static storage
elements. These values are loaded into the FPGA during
configuration and can be reloaded to change the functions
of the programmable elements.

XC5VLX85T-1FFG1136I

Mfr. #:
Manufacturer:
Xilinx
Description:
FPGA - Field Programmable Gate Array BOM fix connect to released FG Part route to Ed Rippert only
Lifecycle:
New from this manufacturer.
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