4
COMMERCIAL TEMPERATURE RANGE
IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™
64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to + 70°C)
Commercial
IDT72420L10 IDT72420L15 IDT72420L25
IDT72200L10 IDT72200L15 IDT72200L25
IDT72210L10 IDT72210L15 IDT72210L25
IDT72220L10 IDT72220L15 IDT72220L25
IDT72230L10 IDT72230L15 IDT72230L25
IDT72240L10 IDT72240L15 IDT72240L25
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
f
S Clock Cycle Frequency 100 66.7 40 MHz
t
A Data Access Time 2 6.5 2 10 2 15 ns
t
CLK Clock Cycle Time 10 15 25 ns
t
CLKH Clock High Time 4.5 6 10 ns
t
CLKL Clock Low Time 4.5 6 10 ns
t
DS Data Setup Time 3 4 6 ns
t
DH Data Hold Time 0.5 1 1 ns
t
ENS Enable Setup Time 3 4 6 ns
t
ENH Enable Hold Time 0.5 1 1 ns
t
RS Reset Pulse Width
(1)
10 15 15 ns
t
RSS Reset Setup Time 8 10 15 ns
t
RSR Reset Recovery Time 8 10 15 ns
t
RSF Reset to Flag and Output Time 10 15 25 ns
t
OLZ Output Enable to Output in Low-Z
(2)
0 0—0—ns
t
OE Output Enable to Output Valid 2 6 3 8 3 13 ns
t
OHZ Output Enable to Output in High-Z
(2)
2 638313ns
t
WFF Write Clock to Full Flag 6.5 10 15 ns
t
REF Read Clock to Empty Flag 6.5 10 15 ns
t
AF Write Clock to Almost-Full Flag 6.5 10 15 ns
t
AE Read Clock to Almost-Empty Flag 6.5 10 15 ns
t
SKEW1 Skew time between Read Clock & Write Clock for 4 6 10 ns
Empty Flag & Full Flag
tSKEW2 Skew time between Read Clock & Write Clock for 10 15 18 ns
Almost-Empty Flag & Almost-Full Flag
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
or equivalent circuit
Figure 1. Output Load
*Includes jig and scope capacitances.
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure 1
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 10 pF
C
OUT Output Capacitance VOUT = 0V 10 pF
(1, 2)
(2)
NOTES:
1. With output deselected. (OE VIH)
2. Characterized values, not currently tested.
AC TEST CONDITIONS
CAPACITANCE (TA = +25°C, f = 1.0 MHz)
30pF*
1.1KΩ
5V
680Ω
D.U.T.
2680 drw03
5
COMMERCIAL TEMPERATURE RANGE
IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™
64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
When all the data has been read from the FIFO, the Empty Flag (EF) will
go LOW, inhibiting further read operations. Once a valid write operation has
been accomplished, the Empty Flag (EF) will go HIGH after tREF and a valid
read can begin. Read Enable (REN) is ignored when the FIFO is empty.
OUTPUT ENABLE (OE) — When Output Enable (OE) is enabled (LOW),
the parallel output buffers receive data from the output register. When
Output Enable (OE) is disabled (HIGH), the Q output data bus is in a high-
impedance state.
OUTPUTS:
FULL FLAG (FF) — The Full Flag (FF) will go LOW, inhibiting further write
operation, when the device is full. If no reads are performed after Reset
(RS), the Full Flag (FF) will go LOW after 64 writes for the IDT72420, 256
writes for the IDT72200, 512 writes for the IDT72210, 1,024 writes for the
IDT72220, 2,048 writes for the IDT72230, and 4,096 writes for the IDT72240.
The Full Flag (FF) is synchronized with respect to the LOW-to-HIGH
transition of the Write Clock (WCLK).
EMPTY FLAG (EF) — The Empty Flag (EF) will go LOW, inhibiting further
read operations, when the read pointer is equal to the write pointer,
indicating the device is empty.
The Empty Flag (EF) is synchronized with respect to the LOW-to-HIGH
transition of the Read Clock (RCLK).
ALMOST-FULL FLAG (AF) — The Almost-Full Flag (AF) will go LOW when
the FIFO reaches the almost-full condition. If no reads are performed after
Reset (RS), the Almost-Full Flag (AF) will go LOW after 57 writes for the
IDT72420, 249 writes for the IDT72200, 505 writes for the IDT72210, 1,017
writes for the IDT72220, 2,041 writes for the IDT72230 and 4,089 writes for
the IDT72240.
The Almost-Full Flag (AF) is synchronized with respect to the LOW-to-
HIGH transition of the Write Clock (WCLK).
ALMOST-EMPTY FLAG (AE) — The Almost-Empty Flag (AE) will go LOW
when the FIFO reaches the almost-empty condition. If no reads are
performed after Reset (RS), the Almost-Empty Flag (AE) will go HIGH after
8 writes for the IDT72420, IDT72200, IDT72210, IDT72220, IDT72230 and
IDT72240.
The Almost-Empty Flag (AE) is synchronized with respect to the LOW-
to-HIGH transition of the Read Clock (RCLK).
DATA OUTPUTS (Q0–Q7) — Data outputs for 8-bit wide data.
SIGNAL DESCRIPTIONS
INPUTS:
Data In (D0–D7) Data inputs for 8-bit wide data.
CONTROLS:
RESET (RS) — Reset is accomplished whenever the Reset (RS) input is
taken to a LOW state. During reset, both internal read and write pointers are
set to the first location. A reset is required after power up before a write
operation can take place. The Full Flag (FF) and Almost-Full Flag (AF) will
be reset to HIGH after tRSF. The Empty Flag (EF) and Almost-Empty Flag
(AE) will be reset to LOW after tRSF. During reset, the output register is
initialized to all zeros.
WRITE CLOCK (WCLK) — A write cycle is initiated on the LOW-to-HIGH
transition of the Write Clock (WCLK). Data setup and hold times must be met
in respect to the LOW-to-HIGH transition of the Write Clock. The Full Flag
(FF) and Almost-Full Flag (AF) are synchronized with respect to the LOW-
to-HIGH transition of the Write Clock.
The Write and Read Clocks can be asynchronous or coincident.
WRITE ENABLE (WEN) — When Write Enable (WEN) is LOW, data can
be loaded into the input register and RAM array on the LOW-to-HIGH
transition of every Write Clock (WCLK). Data is stored in the RAM array
sequentially and independently of any on-going read operation.
When Write Enable (WEN) is HIGH, the input register holds the previous
data and no new data is allowed to be loaded into the register.
To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting
further write operations. Upon the completion of a valid read cycle, the Full
Flag (FF) will go HIGH after tWFF, allowing a valid write to begin. Write
Enable (WEN) is ignored when the FIFO is full.
READ CLOCK (RCLK) — Data can be read on the outputs on the LOW-to-
HIGH transition of the Read Clock (RCLK). The Empty Flag (EF) and
Almost-Empty flag (AE) are synchronized with respect to the LOW-to-HIGH
transition of the Read Clock.
The Write and Read Clocks can be asynchronous or coincident.
READ ENABLE (REN) — When Read Enable (REN) is LOW, data is read
from the RAM array to the output register on the LOW-to-HIGH transition of
the Read Clock (RCLK).
When Read Enable (REN) is HIGH, the output register holds the
previous data and no new data is allowed to be loaded into the register.
Number of Words in FIFO
IDT72420 IDT72200 IDT72210 IDT72220 IDT72230 IDT72240 FF AF AE EF
0000 0 0HHLL
1 to 7 1 to 7 1 to 7 1 to 7 1 to 7 1 to 7 H H L H
8 to 56 8 to 248 8 to 504 8 to 1,016 8 to 2,040 8 to 4,088 HHHH
57 to 63 249 to 255 505 to 511 1,017 to 1,023 2,041 to 2,047 4,089 to 4,095 H L H H
64 256 512 1,024 2,048 4,096 L L H H
TABLE 1 — STATUS FLAGS
6
COMMERCIAL TEMPERATURE RANGE
IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™
64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between the rising edge of RCLK and the
rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
Figure 3. Write Cycle Timing
NOTES:
1. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
2. The Clocks (RCLK, WCLK) can be free-running during reset.
Figure 2. Reset Timing
tRS
tRSR
RS
REN
tRSF
tRSF
EF, AE
FF, AF
Q
0 - Q7
WEN
tRSS
tRSF
tRSR
tRSS
OE = 1
(1)
OE = 0
2680 drw 04
WCLK
D
0
- D
7
WEN
FF
t
CLK
t
CLKH
t
CLKL
t
DS
t
ENS
t
DH
t
ENH
t
WFF
t
WFF
DATA IN VALID
RCLK
(1)
t
SKEW1
REN
NO OPERATION
2680 drw 05

72240L10TPG

Mfr. #:
Manufacturer:
IDT
Description:
FIFO 4K x 8 SyncFIFO 5.0V 10ns 8-bit port
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union